Datasheet

I/O Registers
MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4
Freescale Semiconductor 205
In LIN (version 1.2) systems, the master node transmits a break character which will appear as
11.05–14.95 dominant bits to the slave node. A data character of 0x00 sent from the master might
appear as 7.65–10.35 dominant bit times. This is due to the oscillator tolerance requirement that the
slave node must be within ±15% of the master node's oscillator. Since a slave node cannot know if it
is running faster or slower than the master node (prior to synchronization), the LINR bit allows the slave
node to differentiate between a 0x00 character of 10.35 bits and a break character of 11.05 bits. The
break symbol length must be verified in software in any case, but the LINR bit serves as a filter,
preventing false detections of break characters that are really 0x00 data characters.
SCP1 and SCP0 — ESCI Baud Rate Register Prescaler Bits
These read/write bits select the baud rate register prescaler divisor as shown in Table 15-7. Reset
clears SCP1 and SCP0.
SCR2–SCR0 — ESCI Baud Rate Select Bits
These read/write bits select the ESCI baud rate divisor as shown in Table 15-8. Reset clears
SCR2–SCR0.
Table 15-6. ESCI LIN Control Bits
LINT LINR M Functionality
0 0 X Normal ESCI functionality
0 1 0 13-bit break detect enabled for LIN receiver
0 1 1 14-bit break detect enabled for LIN receiver
1 0 0 13-bit generation enabled for LIN transmitter
1 0 1 14-bit generation enabled for LIN transmitter
1 1 0 13-bit break detect/11-bit generation enabled for LIN
1 1 1 14-bit break detect/12-bit generation enabled for LIN
Table 15-7. ESCI Baud Rate Prescaling
SCP[1:0]
Baud Rate Register
Prescaler Divisor (BPD)
00 1
01 3
10 4
11 13
Table 15-8. ESCI Baud Rate Selection
SCR[2:1:0] Baud Rate Divisor (BD)
000 1
001 2
010 4
011 8
100 16
101 32
110 64
111 128