Datasheet

Enhanced Serial Communications Interface (ESCI) Module
MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4
210 Freescale Semiconductor
ARUN— Arbiter Counter Running Flag
This read-only bit indicates the arbiter counter is running. Reset clears ARUN.
1 = Arbiter counter running
0 = Arbiter counter stopped
AROVFL— Arbiter Counter Overflow Bit
This read-only bit indicates an arbiter counter overflow. Clear AROVFL by writing any value to
SCIACTL. Writing logic 0s to AM1 and AM0 resets the counter keeps it in this idle state. Reset clears
AROVFL.
1 = Arbiter counter overflow has occurred
0 = No arbiter counter overflow has occurred
ARD8— Arbiter Counter MSB
This read-only bit is the MSB of the 9-bit arbiter counter. Clear ARD8 by writing any value to SCIACTL.
Reset clears ARD8.
15.9.2 ESCI Arbiter Data Register
ARD7–ARD0 — Arbiter Least Significant Counter Bits
These read-only bits are the eight LSBs of the 9-bit arbiter counter. Clear ARD7–ARD0 by writing any
value to SCIACTL. Writing logic 0s to AM1 and AM0 permanently resets the counter and keeps it in
this idle state. Reset clears ARD7–ARD0.
15.9.3 Bit Time Measurement
Two bit time measurement modes, described here, are available according to the state of ACLK.
1. ACLK = 0 — The counter is clocked with the bus clock divided by four. The counter is started when
a falling edge on the RxD pin is detected. The counter will be stopped on the next falling edge.
ARUN is set while the counter is running, AFIN is set on the second falling edge on RxD (for
instance, the counter is stopped). This mode is used to recover the received baud rate. See
Figure 15-21.
2. ACLK = 1 — The counter is clocked with one quarter of the ESCI input clock generated by the ESCI
prescaler. The counter is started when a logic 0 is detected on RxD (see Figure 15-22). A logic 0
on RxD on enabling the bit time measurement with ACLK = 1 leads to immediate start of the
counter (see Figure 15-23). The counter will be stopped on the next rising edge of RxD. This mode
is used to measure the length of a received break.
Address: $000B
Bit 7654321Bit 0
Read: ARD7 ARD6 ARD5 ARD4 ARD3 ARD2 ARD1 ARD0
Write:
Reset:00000000
= Unimplemented
Figure 15-20. ESCI Arbiter Data Register (SCIADAT)