Datasheet

System Integration Module (SIM)
MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4
218 Freescale Semiconductor
16.3.2.2 Computer Operating Properly (COP) Reset
An input to the SIM is reserved for the COP reset signal. The overflow of the COP counter causes an
internal reset and sets the COP bit in the SIM reset status register (SRSR). The SIM actively pulls down
the RST
pin for all internal reset sources.
The COP module is disabled if the RST
pin or the IRQ pin is held at V
TST
while the MCU is in monitor
mode. The COP module can be disabled only through combinational logic conditioned with the high
voltage signal on the RST
or the IRQ pin. This prevents the COP from becoming disabled as a result of
external noise. During a break state, V
TST
on the RST pin disables the COP module.
Figure 16-7. POR Recovery
16.3.2.3 Illegal Opcode Reset
The SIM decodes signals from the CPU to detect illegal instructions. An illegal instruction sets the ILOP
bit in the SIM reset status register (SRSR) and causes a reset.
If the stop enable bit, STOP, in the mask option register is logic 0, the SIM treats the STOP instruction as
an illegal opcode and causes an illegal opcode reset. The SIM actively pulls down the RST
pin for all
internal reset sources.
16.3.2.4 Illegal Address Reset
An opcode fetch from an unmapped address generates an illegal address reset. The SIM verifies that the
CPU is fetching an opcode prior to asserting the ILAD bit in the SIM reset status register (SRSR) and
resetting the MCU. A data fetch from an unmapped address does not generate a reset. The SIM actively
pulls down the RST
pin for all internal reset sources.
16.3.2.5 Low-Voltage Inhibit (LVI) Reset
The low-voltage inhibit module (LVI) asserts its output to the SIM when the V
DD
voltage falls to the
LVI
TRIPF
voltage. The LVI bit in the SIM reset status register (SRSR) is set, and the external reset pin
(RST
) is held low while the SIM counter counts out 4096 + 32 CGMXCLK cycles. Thirty-two CGMXCLK
cycles later, the CPU is released from reset to allow the reset vector sequence to occur. The SIM actively
pulls down the RST
pin for all internal reset sources.
PORRST
OSC1
CGMXCLK
CGMOUT
RST
IAB
4096
CYCLES
32
CYCLES
$FFFE $FFFF