Datasheet

Serial Peripheral Interface (SPI) Module
MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4
238 Freescale Semiconductor
Figure 17-8. Transmission Start Delay (Master)
The internal SPI clock in the master is a free-running derivative of the internal MCU clock. To conserve
power, it is enabled only when both the SPE and SPMSTR bits are set. SPSCK edges occur halfway
through the low time of the internal MCU clock. Since the SPI clock is free-running, it is uncertain where
the write to the SPDR occurs relative to the slower SPSCK. This uncertainty causes the variation in the
initiation delay shown in Figure 17-8. This delay is no longer than a single SPI bit time. That is, the
maximum delay is two MCU bus cycles for DIV2, eight MCU bus cycles for DIV8, 32 MCU bus cycles for
DIV32, and 128 MCU bus cycles for DIV128.
WRITE
TO SPDR
INITIATION DELAY
BUS
MOSI
SPSCK
CPHA = 1
SPSCK
CPHA = 0
SPSCK CYCLE
NUMBER
MSB BIT 6
12
CLOCK
WRITE
TO SPDR
EARLIEST
LATEST
SPSCK = INTERNAL CLOCK ÷ 2;
EARLIEST LATEST
2 POSSIBLE START POINTS
SPSCK = INTERNAL CLOCK ÷ 8;
8 POSSIBLE START POINTS
EARLIEST LATESTSPSCK = INTERNAL CLOCK ÷ 32;
32 POSSIBLE START POINTS
EARLIEST LATESTSPSCK = INTERNAL CLOCK ÷ 128;
128 POSSIBLE START POINTS
WRITE
TO SPDR
WRITE
TO SPDR
WRITE
TO SPDR
BUS
CLOCK
BIT 5
3
BUS
CLOCK
BUS
CLOCK
BUS
CLOCK
INITIATION DELAY FROM WRITE SPDR TO TRANSFER BEGIN