Datasheet

Clock Generator Module (CGM)
MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4
64 Freescale Semiconductor
In cases where desired bus frequency has some tolerance, choose f
RCLK
to a value determined
either by other module requirements (such as modules which are clocked by CGMXCLK), cost
requirements, or ideally, as high as the specified range allows. See Chapter 21 Electrical
Specifications. After choosing N, the actual bus frequency can be determined using equation in 2
above.
4. Select a VCO frequency multiplier, N.
5. Calculate and verify the adequacy of the VCO and bus frequencies f
VCLK
and f
BUS
.
6. Select the VCO’s power-of-two range multiplier E, according to Table 4-2.
7. Select a VCO linear range multiplier, L, where f
NOM
= 71.4 kHz
8. Calculate and verify the adequacy of the VCO programmed center-of-range frequency, f
VRS
. The
center-of-range frequency is the midpoint between the minimum and maximum frequencies
attainable by the PLL.
f
VRS
= (L x 2
E
) f
NOM
9. For proper operation,
10. Verify the choice of N, E, and L by comparing f
VCLK
to f
VRS
and f
VCLKDES
. For proper operation,
f
VCLK
must be within the application’s tolerance of f
VCLKDES
, and f
VRS
must be as close as possible
to f
VCLK
.
NOTE
Exceeding the recommended maximum bus frequency or VCO frequency
can crash the MCU.
Table 4-2. Power-of-Two Range Selectors
Frequency Range E
0 < f
VCLK
≤ 8 MHz
0
8 MHz< f
VCLK
≤ 16 MHz
1
16 MHz< f
VCLK
≤ 32 MHz
2
(1)
1. Do not program E to a value of 3.
N round
f
VCLKDES
f
RCLK
--------------------------
⎝⎠
⎜⎟
⎛⎞
=
f
VCLK
N() f
RCLK
×=
f
BUS
f
VCLK
()4⁄=
L = Round
f
VCLK
2
E
x f
NOM
f
VRS
f
VCLK
–
f
NOM
2
E
×
2
---------------------------
≤