Datasheet

MSCAN08 Controller (MSCAN08)
MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4
130 Freescale Semiconductor
12.7 Protocol Violation Protection
The MSCAN08 will protect the user from accidentally violating the CAN protocol through programming
errors. The protection logic implements the following features:
• The receive and transmit error counters cannot be written or otherwise manipulated.
• All registers which control the configuration of the MSCAN08 can not be modified while the
MSCAN08 is on-line. The SFTRES bit in the MSCAN08 module control register (see 12.13.1
MSCAN08 Module Control Register 0) serves as a lock to protect the following registers:
– MSCAN08 module control register 1 (CMCR1)
– MSCAN08 bus timing register 0 and 1 (CBTR0 and CBTR1)
– MSCAN08 identifier acceptance control register (CIDAC)
– MSCAN08 identifier acceptance registers (CIDAR0–3)
– MSCAN08 identifier mask registers (CIDMR0–3)
•The CAN
TX
pin is forced to recessive when the MSCAN08 is in any of the low-power modes.
12.8 Low-Power Modes
In addition to normal mode, the MSCAN08 has three modes with reduced power consumption: sleep, soft
reset, and power down. In sleep and soft reset mode, power consumption is reduced by stopping all
clocks except those to access the registers. In power-down mode, all clocks are stopped and no power
is consumed.
The WAIT and STOP instructions put the MCU in low-power consumption stand-by modes. Table 12-2
summarizes the combinations of MSCAN08 and CPU modes. A particular combination of modes is
entered for the given settings of the bits SLPAK and SFTRES. For all modes, an MSCAN08 wakeup
interrupt can occur only if SLPAK = WUPIE = 1.
Table 12-1. MSCAN08 Interrupt Vector Addresses
Function Source
Local
Mask
Global
Mask
Wakeup WUPIF WUPIE
I bit
Error interrupts
RWRNIF RWRNIE
TWRNIF TWRNIE
RERRIF RERRIE
TERRIF TERRIE
BOFFIF BOFFIE
OVRIF OVRIE
Receive RXF RXFIE
Transmit
TXE0 TXEIE0
TXE1 TXEIE1
TXE2 TXEIE2