Datasheet

MSCAN08 Controller (MSCAN08)
MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4
146 Freescale Semiconductor
12.13.5 MSCAN08 Receiver Flag Register (CRFLG)
All bits of this register are read and clear only. A flag can be cleared by writing a 1 to the corresponding
bit position. A flag can be cleared only when the condition which caused the setting is valid no more.
Writing a 0 has no effect on the flag setting. Every flag has an associated interrupt enable flag in the
CRIER register. A hard or soft reset will clear the register.
WUPIF — Wakeup Interrupt Flag
If the MSCAN08 detects bus activity while in sleep mode, it sets the WUPIF flag. If not masked, a
wakeup interrupt is pending while this flag is set.
1 = MSCAN08 has detected activity on the bus and requested wakeup.
0 = No wakeup interrupt has occurred.
RWRNIF — Receiver Warning Interrupt Flag
This flag is set when the MSCAN08 goes into warning status due to the receive error counter (REC)
exceeding 96 and neither one of the error interrupt flags or the bus-off interrupt flag is set
(1)
. If not
masked, an error interrupt is pending while this flag is set.
1 = MSCAN08 has gone into receiver warning status.
0 = No receiver warning status has been reached.
Table 12-8. Time Segment Values
TSEG13 TSEG12 TSEG11 TSEG10
Time
Segment 1
TSEG22 TSEG21 TSEG20
Time
Segment 2
0000
1 T
q
Cycle
(1)
1. This setting is not valid. Please refer to Table 12-4 for valid settings.
000
1 T
q
Cycle
(1)
0001
2 T
q
Cycles
(1)
001
2 T
q
Cycles
0010
3T
q
Cycles
(1)
... .
0011
4 T
q
Cycles
... .
.... . 111
8T
q
Cycles
.... .
1111
16 T
q
Cycles
Address: $0504
Bit 7654321Bit 0
Read:
WUPIF RWRNIF TWRNIF RERRIF TERRIF BOFFIF OVRIF RXF
Write:
Reset:00000000
Figure 12-20. Receiver Flag Register (CRFLG)
1. Condition to set the flag: RWRNIF = (96 → REC) & RERRIF & TERRIF & BOFFIF