Datasheet

Input/Output (I/O) Ports
MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4
168 Freescale Semiconductor
DDRE5–DDRE0 — Data Direction Register E Bits
These read/write bits control port E data direction. Reset clears DDRE5–DDRE0, configuring all port
E pins as inputs.
1 = Corresponding port E pin configured as output
0 = Corresponding port E pin configured as input
NOTE
Avoid glitches on port E pins by writing to the port E data register before
changing data direction register E bits from 0 to 1.
Figure 13-19 shows the port E I/O logic.
Figure 13-19. Port E I/O Circuit
When bit DDREx is a logic 1, reading address $0008 reads the PTEx data latch. When bit DDREx is a
logic 0, reading address $0008 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 13-6 summarizes the operation of the port E pins.
Address: $000C
Bit 7654321Bit 0
Read: 0 0
DDRE5 DDRE4 DDRE3 DDRE2 DDRE1 DDRE0
Write:
Reset:00000000
= Unimplemented
Figure 13-18. Data Direction Register E (DDRE)
Table 13-6. Port E Pin Functions
DDRE
Bit
PTE
Bit
I/O Pin
Mode
Accesses to DDRE Accesses to PTE
Read/Write Read Write
0
X
(1)
1. X = Don’t care
Input, Hi-Z
(2)
2. Hi-Z = High impedance
DDRE5–DDRE0 Pin
PTE5–PTE0
(3)
3. Writing affects data register, but does not affect input.
1 X Output DDRE5–DDRE0 PTE5–PTE0 PTE5–PTE0
READ DDRE ($000C)
WRITE DDRE ($000C)
RESET
WRITE PTE ($0008)
READ PTE ($0008)
PTEx
DDREx
PTEx
INTERNAL DATA BUS