Datasheet

System Integration Module (SIM)
MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4
214 Freescale Semiconductor
The SIM is responsible for:
• Bus clock generation and control for CPU and peripherals:
– Stop/wait/reset/break entry and recovery
– Internal clock control
• Master reset control, including power-on reset (POR) and computer operating properly (COP)
timeout
• Interrupt control:
– Acknowledge timing
– Arbitration control timing
– Vector address generation
• CPU enable/disable timing
• Modular architecture expandable to 128 interrupt sources
Table 16-1 shows the internal signal names used in this section.
Table 16-1. Signal Name Conventions
Signal Name Description
CGMXCLK Buffered version of OSC1 from clock generator module (CGM)
CGMVCLK PLL output
CGMOUT PLL-based or OSC1-based clock output from CGM module (Bus clock = CGMOUT divided by two)
IAB Internal address bus
IDB Internal data bus
PORRST Signal from the power-on reset module to the SIM
IRST Internal reset signal
R/W
Read/write signal
Addr.Register Name Bit 7654321Bit 0
$FE00
SIM Break Status
Register (SBSR)
See page 228.
Read:
RRRRRR
SBSW
R
Write: Note
(1)
Reset:00000000
1. Writing a logic 0 clears SBSW.
$FE01
SIM Reset Status
Register (SRSR)
See page 228.
Read: POR PIN COP ILOP ILAD MODRST LVI 0
Write:
POR:10000000
$FE03
SIM Break Flag Control
Register (SBFCR)
See page 229.
Read:
BCFERRRRRRR
Write:
Reset: 0
$FE04
Interrupt Status
Register 1 (INT1)
See page 224.
Read: IF6 IF5 IF4 IF3 IF2 IF1 0 0
Write:RRRRRRRR
Reset:00000000
$FE05
Interrupt Status
Register 2 (INT2)
See page 224.
Read: IF14 IF13 IF12 IF11 IF10 IF9 IF8 IF7
Write:RRRRRRRR
Reset:00000000
$FE06
Interrupt Status
Register 3 (INT3)
See page 224.
Read: 0 0 IF20 IF19 IF18 IF17 IF16 IF15
Write:RRRRRRRR
Reset:00000000
= Unimplemented R = Reserved
Figure 16-2. SIM I/O Register Summary