Datasheet

System Integration Module (SIM)

MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4

216 Freescale Semiconductor

16.3 Reset and System Initialization

The MCU has these reset sources:

• Power-on reset module (POR)

• External reset pin (RST

)

• Computer operating properly module (COP)

• Low-voltage inhibit module (LVI)

• Illegal opcode

• Illegal address

• Forced monitor mode entry reset (MODRST)

All of these resets produce the vector $FFFE:$FFFF ($FEFE:$FEFF in monitor mode) and assert the

internal reset signal (IRST). IRST causes all registers to be returned to their default values and all

modules to be returned to their reset states.

An internal reset clears the SIM counter (see 16.4 SIM Counter), but an external reset does not. Each of

the resets sets a corresponding bit in the SIM reset status register (SRSR). See 16.7 SIM Registers.

16.3.1 External Pin Reset

The RST pin circuit includes an internal pullup device. Pulling the asynchronous RST pin low halts all

processing. The PIN bit of the SIM reset status register (SRSR) is set as long as RST

is held low for a

minimum of 67 CGMXCLK cycles, assuming that neither the POR nor the LVI was the source of the reset.

See Table 16-2 for details. Figure 16-4 shows the relative timing.

Figure 16-4. External Reset Timing

Table 16-2. PIN Bit Set Timing

Reset Type Number of Cycles Required to Set PIN

POR/LVI 4163 (4096 + 64 + 3)

All others 67 (64 + 3)

RST

IAB

VECT H VECT L

CGMOUT