Datasheet

System Integration Module (SIM)
MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4
226 Freescale Semiconductor
Figure 16-15. Wait Mode Entry Timing
Figure 16-16 and Figure 16-17 show the timing for WAIT recovery.
Figure 16-16. Wait Recovery from Interrupt
Figure 16-17. Wait Recovery from Internal Reset
16.6.2 Stop Mode
In stop mode, the SIM counter is reset and the system clocks are disabled. An interrupt request from a
module can cause an exit from stop mode. Stacking for interrupts begins after the selected stop recovery
time has elapsed. Reset causes an exit from stop mode.
The SIM disables the clock generator module outputs (CGMOUT and CGMXCLK) in stop mode, stopping
the CPU and peripherals. Stop recovery time is selectable using the SSREC bit in the mask option register
(MOR). If SSREC is set, stop recovery is reduced from the normal delay of 4096 CGMXCLK cycles down
to 32. This is ideal for applications using canned oscillators that do not require long startup times from
stop mode.
WAIT ADDR + 1 SAME SAMEIAB
IDB
PREVIOUS DATA NEXT OPCODE SAME
WAIT ADDR
SAME
R/W
Note: Previous data can be operand data or the WAIT opcode, depending on the
last instruction.
$6E0C$6E0B $00FF $00FE $00FD $00FC
$A6 $A6 $01 $0B $6E$A6
IAB
IDB
EXITSTOPWAIT
Note: EXITSTOPWAIT = RST pin or CPU interrupt
IAB
IDB
RST
$A6 $A6
$6E0B
RST VCT H RST VCT L
$A6
CGMXCLK
32
CYCLES
32
CYCLES