Datasheet

Interrupts
MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4
Freescale Semiconductor 243
17.8 Interrupts
Four SPI status flags can be enabled to generate CPU interrupt requests. See Table 17-2.
Reading the SPI status and control register with SPRF set and then reading the receive data register
clears SPRF. The clearing mechanism for the SPTE flag is always just a write to the transmit data register.
The SPI transmitter interrupt enable bit (SPTIE) enables the SPTE flag to generate transmitter CPU
interrupt requests, provided that the SPI is enabled (SPE = 1).
The SPI receiver interrupt enable bit (SPRIE) enables the SPRF bit to generate receiver CPU interrupt
requests, regardless of the state of the SPE bit. See Figure 17-12.
The error interrupt enable bit (ERRIE) enables both the MODF and OVRF bits to generate a receiver/error
CPU interrupt request.
The mode fault enable bit (MODFEN) can prevent the MODF flag from being set so that only the OVRF
bit is enabled by the ERRIE bit to generate receiver/error CPU interrupt requests.
Figure 17-12. SPI Interrupt Request Generation
Table 17-2. SPI Interrupts
Flag Request
SPTE
Transmitter empty
SPI transmitter CPU interrupt request
(SPTIE = 1, SPE = 1)
SPRF
Receiver full
SPI receiver CPU interrupt request
(SPRIE = 1)
OVRF
Overflow
SPI receiver/error interrupt request
(ERRIE = 1)
MODF
Mode fault
SPI receiver/error interrupt request
(ERRIE = 1)
SPTE SPTIE
SPRFSPRIE
SPE
CPU INTERRUPT REQUEST
CPU INTERRUPT REQUEST
NOT AVAILABLE
SPI TRANSMITTER
NOT AVAILABLE
SPI RECEIVER/ERROR
ERRIE
MODF
OVRF