Datasheet

Serial Peripheral Interface (SPI) Module
MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4
250 Freescale Semiconductor
MODFEN — Mode Fault Enable Bit
This read/write bit, when set to 1, allows the MODF flag to be set. If the MODF flag is set, clearing the
MODFEN does not clear the MODF flag. If the SPI is enabled as a master and the MODFEN bit is low,
then the SS
pin is available as a general-purpose I/O.
If the MODFEN bit is set, then this pin is not available as a general-purpose I/O. When the SPI is
enabled as a slave, the SS
pin is not available as a general-purpose I/O regardless of the value of
MODFEN. See 17.12.4 SS (Slave Select).
If the MODFEN bit is low, the level of the SS
pin does not affect the operation of an enabled SPI
configured as a master. For an enabled SPI configured as a slave, having MODFEN low only prevents
the MODF flag from being set. It does not affect any other part of SPI operation. See 17.7.2 Mode Fault
Error.
SPR1 and SPR0 — SPI Baud Rate Select Bits
In master mode, these read/write bits select one of four baud rates as shown in Table 17-4. SPR1 and
SPR0 have no effect in slave mode. Reset clears SPR1 and SPR0.
Use this formula to calculate the SPI baud rate:
where:
CGMOUT = base clock output of the clock generator module (CGM)
BD = baud rate divisor
17.13.3 SPI Data Register
The SPI data register consists of the read-only receive data register and the write-only transmit data
register. Writing to the SPI data register writes data into the transmit data register. Reading the SPI data
register reads data from the receive data register. The transmit data and receive data registers are
separate registers that can contain different values. See Figure 17-3.
R7–R0/T7–T0 — Receive/Transmit Data Bits
NOTE
Do not use read-modify-write instructions on the SPI data register since the
register read is not the same as the register written.
Table 17-4. SPI Master Baud Rate Selection
SPR1 and SPR0 Baud Rate Divisor (BD)
00 2
01 8
10 32
11 128
Address: $0012
Bit 7654321Bit 0
Read:R7R6R5R4R3R2R1R0
Write: T7 T6 T5 T4 T3 T2 T1 T0
Reset: Unaffected by reset
Figure 17-16. SPI Data Register (SPDR)
Baud rate
CGMOUT
2BD×
--------------------------=