Datasheet

CGM Registers
MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4
Freescale Semiconductor 69
4.5.1 PLL Control Register
The PLL control register (PCTL) contains the interrupt enable and flag bits, the on/off switch, the base
clock selector bit, and the VCO power-of-two range selector bits.
Addr.Register Name Bit 7654321Bit 0
$0036
PLL Control Register
(PCTL)
See page 69.
Read:
PLLIE
PLLF
PLLON BCS R R VPR1 VPR0
Write:
Reset:00100000
$0037
PLL Bandwidth Control
Register (PBWC)
See page 71.
Read:
AUTO
LOCK
ACQ
0000
R
Write:
Reset:00000000
$0038
PLL Multiplier Select High
Register (PMSH)
See page 72.
Read:0000
MUL11 MUL10 MUL9 MUL8
Write:
Reset:00000000
$0039
PLL Multiplier Select Low
Register (PMSL)
See page 73.
Read:
MUL7 MUL6 MUL5 MUL4 MUL3 MUL2 MUL1 MUL0
Write:
Reset:01000000
$003A
PLL VCO Select Range
Register (PMRS)
See page 73.
Read:
VRS7 VRS6 VRS5 VRS4 VRS3 VRS2 VRS1 VRS0
Write:
Reset:01000000
$003B Reserved Register
Read:0000
RRRR
Write:
Reset:00000001
= Unimplemented R = Reserved
NOTES:
1. When AUTO = 0, PLLIE is forced clear and is read-only.
2. When AUTO = 0, PLLF and LOCK read as clear.
3. When AUTO = 1, ACQ
is read-only.
4. When PLLON = 0 or VRS7:VRS0 = $0, BCS is forced clear and is read-only.
5. When PLLON = 1, the PLL programming register is read-only.
6. When BCS = 1, PLLON is forced set and is read-only.
Figure 4-3. CGM I/O Register Summary
Address: $0036
Bit 7 6 5 4 3 2 1 Bit 0
Read:
PLLIE
PLLF
PLLON BCS R R VPR1 VPR0
Write:
Reset:00100 0 00
= Unimplemented R = Reserved
Figure 4-4. PLL Control Register (PCTL)