Datasheet

Enhanced Serial Communications Interface (ESCI) Module
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
194 Freescale Semiconductor
14.4.2 Transmitter
Figure 14-5 shows the structure of the SCI transmitter and the registers are summarized in Figure 14-4.
The baud rate clock source for the ESCI can be selected via the configuration bit, SCIBDSRC.
Figure 14-5. ESCI Transmitter
14.4.2.1 Character Length
The transmitter can accommodate either 8-bit or 9-bit data. The state of the M bit in ESCI control
register 1 (SCC1) determines character length. When transmitting 9-bit data, bit T8 in ESCI control
register 3 (SCC3) is the ninth bit (bit 8).
14.4.2.2 Character Transmission
During an ESCI transmission, the transmit shift register shifts a character out to the TxD pin. The ESCI
data register (SCDR) is the write-only buffer between the internal data bus and the transmit shift register.
PEN
PTY
H876543210L
11-BIT
TRANSMIT
STOP START
T8
SCTE
SCTIE
TCIE
SBK
TC
PARITY
GENERATION
MSB
ESCI DATA REGISTER
LOAD FROM SCDR SHIFT ENABLE
PREAMBLE
(ALL ONES)
BREAK
(ALL ZEROS)
TRANSMITTER
CONTROL LOGIC
SHIFT REGISTER
TC
SCTIE
TCIE
SCTE
M
ENSCI
LOOPS
TE
TXINV
INTERNAL BUS
÷ 4
PRE-
SCALER
SCP1
SCP0
SCR1
SCR2
SCR0
BAUD
DIVIDER
÷ 16
SCI_TxD
PRE-
SCALER
PDS1
PDS2
PDS0
PSSB3
PSSB4
PSSB2
PSSB1
PSSB0
LINT
TRANSMITTER CPU
INTERRUPT REQUEST
CGMXCLK
OR
BUS CLOCK