Datasheet

Enhanced Serial Communications Interface (ESCI) Module
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
214 Freescale Semiconductor
14.8.8 ESCI Prescaler Register
The ESCI prescaler register (SCPSC) together with the ESCI baud rate register selects the baud rate for
both the receiver and the transmitter.
NOTE
There are two prescalers available to adjust the baud rate. One in the ESCI
baud rate register and one in the ESCI prescaler register.
;
PDS2–PDS0 — Prescaler Divisor Select Bits
These read/write bits select the prescaler divisor as shown in Table 14-9. Reset clears PDS2–PDS0.
NOTE
The setting of ‘000’ will bypass not only this prescaler but also the prescaler
divisor fine adjust (PDFA). It is not recommended to bypass the prescaler
while ENSCI is set, because the switching is not glitch free.
PSSB4–PSSB0 — Clock Insertion Select Bits
These read/write bits select the number of clocks inserted in each 32 output cycle frame to achieve
more timing resolution on the average prescaler frequency as shown in Table 14-10. Reset clears
PSSB4–PSSB0.
Address: $0009
Bit 7654321Bit 0
Read:
PDS2 PDS1 PDS0 PSSB4 PSSB3 PSSB2 PSSB1 PSSB0
Write:
Reset:00000000
Figure 14-18. ESCI Prescaler Register (SCPSC)
Table 14-9. ESCI Prescaler Division Ratio
PDS[2:1:0] Prescaler Divisor (PD)
0 0 0 Bypass this prescaler
001 2
010 3
011 4
100 5
101 6
110 7
111 8
Table 14-10. ESCI Prescaler Divisor Fine Adjust
PSSB[4:3:2:1:0] Prescaler Divisor Fine Adjust (PDFA)
00000 0/32 = 0
00001 1/32 = 0.03125
00010 2/32 = 0.0625
00011 3/32 = 0.09375
0 0 1 0 0 4/32 = 0.125