Datasheet

ESCI Arbiter
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
Freescale Semiconductor 219
another bus is driving the bus dominant) ALOST is set. As long as ALOST is set, the TxD pin is forced
to 1, resulting in a seized transmission.
If SCI_TxD senses 0 without having sensed a 0 before on RxD, the counter will be reset, arbitration
operation will be restarted after the next rising edge of SCI_TxD.
Figure 14-21. Bit Time Measurement with ACLK = 0
Figure 14-22. Bit Time Measurement with ACLK = 1, Scenario A
Figure 14-23. Bit Time Measurement with ACLK = 1, Scenario B
CPU WRITES SCIACTL
COUNTER STARTS,
COUNTER STOPS,
MEASURED TIME
CPU READS RESULT
RXD
WITH $20
ARUN = 1
AFIN = 1
OUT OF SCIADAT
CPU WRITES SCIACTL WITH $30
COUNTER STARTS, ARUN = 1
COUNTER STOPS, AFIN = 1
MEASURED TIME
CPU READS RESULT OUT
RXD
OF SCIADAT
CPU WRITES SCIACTL
COUNTER STARTS,
COUNTER STOPS,
MEASURED TIME
CPU READS RESULT
RXD
OUT OF SCIADAT
AFIN = 1
ARUN = 1
WITH $30