Datasheet

SIM Registers
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
Freescale Semiconductor 237
15.7.1 Break Status Register
The break status register (BSR) contains a flag to indicate that a break caused an exit from wait mode.
This register is only used in emulation mode.
SBSW — SIM Break Stop/Wait
SBSW can be read within the break state SWI routine. The user can modify the return address on the
stack by subtracting one from it.
1 = Wait mode was exited by break interrupt.
0 = Wait mode was not exited by break interrupt.
15.7.2 SIM Reset Status Register
This register contains six flags that show the source of the last reset provided all previous reset status bits
have been cleared. Clear the SIM reset status register by reading it. A power-on reset sets the POR bit
and clears all other bits in the register.
The register is initialized on power up with the POR bit set and all other bits cleared. During a POR or any
other internal reset, the RST
pin is pulled low. After the pin is released, it will be sampled 32 CGMXCLK
cycles later. If the pin is not above V
IH
at this time, then the PIN bit may be set, in addition to whatever
other bits are set.
POR — Power-On Reset Bit
1 = Last reset caused by POR circuit
0 = Read of SRSR
PIN — External Reset Bit
1 = Last reset caused by external reset pin (RST
)
0 = POR or read of SRSR
COP — Computer Operating Properly Reset Bit
1 = Last reset caused by COP counter
0 = POR or read of SRSR
Address: $FE00
Bit 7654321Bit 0
Read:
RRRRRR
SBSW
R
Write: Note
(1)
Reset:00000000
R = Reserved 1. Writing a 0 clears SBSW.
Figure 15-21. Break Status Register (BSR)
Address: $FE01
Bit 7654321Bit 0
Read: POR PIN COP ILOP ILAD MODRST LVI 0
Write:
Reset:10000000
= Unimplemented
Figure 15-22. SIM Reset Status Register (SRSR)