Datasheet

Low-Power Modes
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
Freescale Semiconductor 261
As an example, a 4.9152 MHz crystal, with the TMBCLKSEL set for divide-by-128 and the TBR2–TBR0
set to {011}, the divider is 16,384 and the interrupt rate calculates to:
NOTE
Do not change TBR2–TBR0 bits while the timebase is enabled (TBON = 1).
17.6 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power- consumption standby modes.
17.6.1 Wait Mode
The timebase module remains active after execution of the WAIT instruction. In wait mode the timebase
register is not accessible by the CPU.
If the timebase functions are not required during wait mode, reduce the power consumption by stopping
the timebase before executing the WAIT instruction.
17.6.2 Stop Mode
The timebase module may remain active after execution of the STOP instruction if the oscillator has been
enabled to operate during stop mode through the OSCENINSTOP bit in the configuration register. The
timebase module can be used in this mode to generate a periodic wakeup from stop mode.
If the oscillator has not been enabled to operate in stop mode, the timebase module will not be active
during stop mode. In stop mode, the timebase register is not accessible by the CPU.
If the timebase functions are not required during stop mode, reduce power consumption by disabling the
timebase module before executing the STOP instruction.
Table 17-1. Timebase Divider Selection
Divider
TBR2 TBR1 TBR0
TMBCLKSEL
01
0 0 0 32,768 4,194,304
0 0 1 8192 1,048,576
0 1 0 2048 262144
0 1 1 128 16,384
1 0 0 64 8192
1 0 1 32 4096
1 1 0 16 2048
1 1 1 8 1024
16,384
4.9152 x 10
6
= 3.33 ms