Datasheet

Input/Output Registers
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
Freescale Semiconductor 273
18.8.2 TIM1 Counter Registers
The two read-only TIM1 counter registers contain the high and low bytes of the value in the TIM1 counter.
Reading the high byte (T1CNTH) latches the contents of the low byte (T1CNTL) into a buffer. Subsequent
reads of T1CNTH do not affect the latched T1CNTL value until T1CNTL is read. Reset clears the TIM1
counter registers. Setting the TIM1 reset bit (TRST) also clears the TIM1 counter registers.
NOTE
If you read T1CNTH during a break interrupt, be sure to unlatch T1CNTL
by reading T1CNTL before exiting the break interrupt. Otherwise, T1CNTL
retains the value latched during the break.
18.8.3 TIM1 Counter Modulo Registers
The read/write TIM1 modulo registers contain the modulo value for the TIM1 counter. When the TIM1
counter reaches the modulo value, the overflow flag (TOF) becomes set, and the TIM1 counter resumes
counting from $0000 at the next timer clock. Writing to the high byte (T1MODH) inhibits the TOF bit and
overflow interrupts until the low byte (T1MODL) is written. Reset sets the TIM1 counter modulo registers.
NOTE
Reset the TIM1 counter before writing to the TIM1 counter modulo registers.
Address:
$0021 T1CNTH
Bit 7654321Bit 0
Read: Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Write:
Reset:00000000
Address:
$0022 T1CNTL
Bit 7654321Bit 0
Read: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Write:
Reset:00000000
= Unimplemented
Figure 18-6. TIM1 Counter Registers (T1CNTH:T1CNTL)
Address: $0023 T1MODH
Bit 7654321Bit 0
Read:
Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8
Write:
Reset:11111111
Address: $0024 T1MODL
Bit 7654321Bit 0
Read:
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Write:
Reset:11111111
Figure 18-7. TIM1 Counter Modulo Registers (T1MODH:T1MODL)