Datasheet

Timer Interface Module (TIM1)
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
274 Freescale Semiconductor
18.8.4 TIM1 Channel Status and Control Registers
Each of the TIM1 channel status and control registers does the following:
• Flags input captures and output compares
• Enables input capture and output compare interrupts
• Selects input capture, output compare, or PWM operation
• Selects high, low, or toggling output on output compare
• Selects rising edge, falling edge, or any edge as the active input capture trigger
• Selects output toggling on TIM1 overflow
• Selects 0% and 100% PWM duty cycle
• Selects buffered or unbuffered output compare/PWM operation
CHxF — Channel x Flag Bit
When channel x is an input capture channel, this read/write bit is set when an active edge occurs on
the channel x pin. When channel x is an output compare channel, CHxF is set when the value in the
TIM1 counter registers matches the value in the TIM1 channel x registers.
Clear CHxF by reading the TIM1 channel x status and control register with CHxF set and then writing
a 0 to CHxF. If another interrupt request occurs before the clearing sequence is complete, then
writing 0 to CHxF has no effect. Therefore, an interrupt request cannot be lost due to inadvertent
clearing of CHxF.
Reset clears the CHxF bit. Writing a 1 to CHxF has no effect.
1 = Input capture or output compare on channel x
0 = No input capture or output compare on channel x
CHxIE — Channel x Interrupt Enable Bit
This read/write bit enables TIM1 CPU interrupt service requests on channel x. Reset clears the CHxIE
bit.
1 = Channel x CPU interrupt requests enabled
0 = Channel x CPU interrupt requests disabled
Address: $0025 T1SC0
Bit 7654321Bit 0
Read: CH0F
CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX
Write: 0
Reset:00000000
Address:
$0028 T1SC1
Bit 7654321Bit 0
Read: CH1F
CH1IE
0
MS1A ELS1B ELS1A TOV1 CH1MAX
Write: 0
Reset:00000000
= Unimplemented
Figure 18-8. TIM1 Channel Status and Control
Registers (T1SC0:T1SC1)