Datasheet

Timer Interface Module (TIM2)
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
294 Freescale Semiconductor
CHxF — Channel x Flag Bit
When channel x is an input capture channel, this read/write bit is set when an active edge occurs on
the channel x pin. When channel x is an output compare channel, CHxF is set when the value in the
TIM2 counter registers matches the value in the TIM2 channel x registers.
When CHxIE = 1, clear CHxF by reading TIM2 channel x status and control register with CHxF set,
and then writing a 0 to CHxF. If another interrupt request occurs before the clearing sequence is
complete, then writing 0 to CHxF has no effect. Therefore, an interrupt request cannot be lost due to
inadvertent clearing of CHxF.
Reset clears the CHxF bit. Writing a 1 to CHxF has no effect.
1 = Input capture or output compare on channel x
0 = No input capture or output compare on channel x
CHxIE — Channel x Interrupt Enable Bit
This read/write bit enables TIM2 CPU interrupts on channel x.
Reset clears the CHxIE bit.
1 = Channel x CPU interrupt requests enabled
0 = Channel x CPU interrupt requests disabled
Address: $0033 T2SC1
Bit 7654321Bit 0
Read: CH1F
CH1IE
0
MS1A ELS1B ELS1A TOV1 CH1MAX
Write: 0
Reset:00000000
Address: $0456 T2SC2
Bit 7654321Bit 0
Read: CH2F
CH2IE MS2B MS2A ELS2B ELS2A TOV2 CH2MAX
Write: 0
Reset:00000000
Address: $0459 T2SC3
Bit 7654321Bit 0
Read: CH3F
CH3IE
0
MS3A ELS3B ELS3A TOV3 CH3MAX
Write: 0
Reset:00000000
Address: $045C T2SC4
Bit 7654321Bit 0
Read: CH4F
CH4IE MS4B MS4A ELS4B ELS4A TOV4 CH4MAX
Write: 0
Reset:00000000
Address: $045F T2SC5
Bit 7654321Bit 0
Read: CH5F
CH5IE
0
MS5A ELS5B ELS5A TOV5 CH5MAX
Write: 0
Reset:00000000
= Unimplemented
Figure 19-8. TIM2 Channel Status and Control Registers
(T2SC0:T2SC5) (Continued)