Datasheet

I/O Registers
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
Freescale Semiconductor 295
MSxB — Mode Select Bit B
This read/write bit selects buffered output compare/PWM operation. MSxB exists only in the TIM2
channel 0, TIM2 channel 2, and TIM2 channel 4 status and control registers.
Setting MS0B disables the channel 1 status and control register and reverts T2CH1 pin to
general-purpose I/O.
Setting MS2B disables the channel 3 status and control register and reverts T2CH3 pin to
general-purpose I/O.
Setting MS4B disables the channel 5 status and control register and reverts T2CH5 pin to
general-purpose I/O.
Reset clears the MSxB bit.
1 = Buffered output compare/PWM operation enabled
0 = Buffered output compare/PWM operation disabled
MSxA — Mode Select Bit A
When ELSxB:ELSxA 00, this read/write bit selects either input capture operation or unbuffered
output compare/PWM operation. (See Table 19-2.)
1 = Unbuffered output compare/PWM operation
0 = Input capture operation
When ELSxB:ELSxA = 00, this read/write bit selects the initial output level of the T2CHx pin once
PWM, input capture, or output compare operation is enabled. (See Table 19-2.) Reset clears the MSxA
bit.
1 = Initial output level low
0 = Initial output level high
NOTE
Before changing a channel function by writing to the MSxB or MSxA bit, set
the TSTOP and TRST bits in the TIM2 status and control register (T2SC).
Table 19-2. Mode, Edge, and Level Selection
MSxB MSxA ELSxB ELSxA Mode Configuration
X0 0 0
Output preset
Pin under port control; initial output level high
X 1 0 0 Pin under port control; initial output level low
00 0 1
Input capture
Capture on rising edge only
0 0 1 0 Capture on falling edge only
0 0 1 1 Capture on rising or falling edge
01 0 0
Output compare
or PWM
Software compare only
0 1 0 1 Toggle output on compare
0 1 1 0 Clear output on compare
0 1 1 1 Set output on compare
1 X 0 1 Buffered
output
compare or
buffered PWM
Toggle output on compare
1 X 1 0 Clear output on compare
1 X 1 1 Set output on compare