Datasheet

5.0-Volt Control Timing
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
Freescale Semiconductor 321
21.7 5.0-Volt Control Timing
21.8 3.3-Volt Control Timing
Figure 21-1. RST and IRQ Timing
Characteristic
(1)
1. V
SS
= 0 Vdc; timing shown with respect to 20% V
DD
and 70% V
DD
unless otherwise noted.
Symbol Min Max Unit
Frequency of operation
Crystal option
External clock option
(2)
2. No more than 10% duty cycle deviation from 50%.
f
OSC
1
dc
8
32
MHz
Internal operating frequency
f
OP
(f
Bus
)
—8MHz
Internal clock period (1/f
OP
)t
CYC
125 — ns
RESET input pulse width low
t
RL
100 — ns
IRQ
interrupt pulse width low (edge-triggered)
t
ILIH
100 — ns
IRQ
interrupt pulse period
(3)
3. The minimum period is the number of cycles it takes to execute the interrupt service routine plus 1 t
CYC
.
t
ILIL
Note 3 —
t
CYC
Characteristic
(1)
1. V
SS
= 0 Vdc; timing shown with respect to 20% V
DD
and 70% V
DD
unless otherwise noted.
Symbol Min Max Unit
Frequency of operation
Crystal option
External clock option
(2)
2. No more than 10% duty cycle deviation from 50%.
f
OSC
1
dc
8
16
MHz
Internal operating frequency
f
OP
(f
Bus
)
—4MHz
Internal clock period (1/f
OP
)t
CYC
250 — ns
RESET input pulse width low
t
RL
200 — ns
IRQ
interrupt pulse width low (edge-triggered)
t
ILIH
200 — ns
IRQ
interrupt pulse period
(3)
3. The minimum period is the number of cycles it takes to execute the interrupt service routine plus 1 t
CYC
.
t
ILIL
Note 3 —
t
CYC
RST
IRQ
t
RL
t
ILIH
t
ILIL