Datasheet

Monotonicity
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
Freescale Semiconductor 65
Left justified sign data mode is similar to left justified mode with one exception. The MSB of the 10-bit
result, AD9 located in ADRH, is complemented. This mode of operation is useful when a result,
represented as a signed magnitude from mid-scale, is needed. Finally, 8-bit truncation mode will place
the eight MSBs in the ADC data register low, ADRL. The two LSBs are dropped. This mode of operation
is used when compatibility with 8-bit ADC designs are required. No interlocking between ADRH and ADRL
is present.
NOTE
Quantization error is affected when only the most significant eight bits are
used as a result. See Figure 3-3.
Figure 3-3. Bit Truncation Mode Error
3.4 Monotonicity
The conversion process is monotonic and has no missing codes.
3.5 Interrupts
When the AIEN bit is set, the ADC module is capable of generating CPU interrupts after each ADC
conversion. A CPU interrupt is generated if the COCO bit is a 0. The COCO bit is not used as a conversion
complete flag when interrupts are enabled.
IDEAL 10-BIT CHARACTERISTIC
WITH QUANTIZATION = ±1/2
IDEAL 8-BIT CHARACTERISTIC
WITH QUANTIZATION = ±1/2
10-BIT TRUNCATED
TO 8-BIT RESULT
WHEN TRUNCATION IS USED,
ERROR FROM IDEAL 8-BIT = 3/8 LSB
DUE TO NON-IDEAL QUANTIZATION.
000
001
002
003
004
005
006
007
008
009
00A
00B
000
001
002
003
8-BIT
RESULT
10-BIT
RESULT
INPUT VOLTAGE
REPRESENTED AS 10-BIT
INPUT VOLTAGE
REPRESENTED AS 8-BIT
1/2 2 1/2 4 1/2 6 1/2 8 1/2
1 1/2 3 1/2 5 1/2 7 1/2 9 1/2
1/2 2 1/21 1/2