Datasheet

Configuration Register (CONFIG)
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
92 Freescale Semiconductor
MCLKSEL — MCLK Source Select Bit
1 = Crystal frequency
0 = Bus frequency
MCLK1 and MCLK0 — MCLK Output Select Bits
Setting the MCLK1 and MCLK0 bits enables the PTD0/SS
pin to be used as a MCLK output clock.
Once configured for MCLK, the PTD data direction register for PTD0 is used to enable and disable the
MCLK output.
See Table 5-1 for MCLK options.
MSCANEN— MSCAN08 Enable Bit
Setting the MSCANEN
enables the MSCAN08 module and allows the MSCAN08 to use the PTC0/PTC1
pins.
See Chapter 12 MSCAN08 Controller (MSCAN08) for a more detailed description of the
MSCAN08 operation.
1 = Enables MSCAN08 module
0 = Disables the MSCAN08 module
NOTE
The MSCANEN bit is cleared by a power-on reset (POR) only. Other resets
will leave this bit unaffected.
TMBCLKSEL— Timebase Clock Select Bit
TMBCLKSEL
enables an extra divide-by-128 prescaler in the timebase module. Setting this bit enables
the extra prescaler and clearing this bit disables it.
See Chapter 17 Timebase Module (TBM) for a more
detailed description of the external clock operation.
1 = Enables extra divide-by-128 prescaler in timebase module
0 = Disables extra divide-by-128 prescaler in timebase module
Address: $001E
Bit 76543 2 1Bit 0
Read: 0
MCLKSEL MCLK1 MCLK0 MSCANEN TMBCLKSEL OSCENINSTOP SCIBDSRC
Write:
Reset:0000See note0 0 1
Note: MSCANEN is only reset via POR (power-on reset).
= Unimplemented
Figure 5-1. Configuration Register 2 (CONFIG2)
Table 5-1. MCLK Output Select
MCLK1 MCLK0 MCLK Frequency
0 0 MCLK not enabled
0 1 Clock
1 0 Clock divided by 2
1 1 Clock divided by 4