Datasheet

Serial Peripheral Interface (SPI) Module
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
254 Freescale Semiconductor
When enabled, the SPI controls data direction of the MOSI pin regardless of the state of the data direction
register of the shared I/O port.
16.11.3 SPSCK (Serial Clock)
The serial clock synchronizes data transmission between master and slave devices. In a master MCU,
the SPSCK pin is the clock output. In a slave MCU, the SPSCK pin is the clock input. In full-duplex
operation, the master and slave MCUs exchange a byte of data in eight serial clock cycles.
When enabled, the SPI controls data direction of the SPSCK pin regardless of the state of the data
direction register of the shared I/O port.
16.11.4 SS (Slave Select)
The SS pin has various functions depending on the current state of the SPI. For an SPI configured as a
slave, the SS
is used to select a slave. For CPHA = 0, the SS is used to define the start of a transmission.
(See 16.4 Transmission Formats.) Since it is used to indicate the start of a transmission, SS
must be
toggled high and low between each byte transmitted for the CPHA = 0 format. However, it can remain low
between transmissions for the CPHA = 1 format. See Figure 16-13.
When an SPI is configured as a slave, the SS
pin is always configured as an input. It cannot be used as
a general-purpose I/O regardless of the state of the MODFEN control bit. However, the MODFEN bit can
still prevent the state of SS
from creating a MODF error. See 16.12.2 SPI Status and Control Register.
Figure 16-13. CPHA/SS
Timing
NOTE
A high on the SS
pin of a slave SPI puts the MISO pin in a high-impedance
state. The slave SPI ignores all incoming SPSCK clocks, even if it was
already in the middle of a transmission.
When an SPI is configured as a master, the SS
input can be used in conjunction with the MODF flag to
prevent multiple masters from driving MOSI and SPSCK. (See 16.6.2 Mode Fault Error.) For the state of
the SS
pin to set the MODF flag, the MODFEN bit in the SPSCK register must be set. If MODFEN is 0 for
an SPI master, the SS
pin can be used as a general-purpose I/O under the control of the data direction
register of the shared I/O port. When MODFEN is 1, SS
is an input-only pin to the SPI regardless of the
state of the data direction register of the shared I/O port.
The CPU can always read the state of the SS
pin by configuring the appropriate pin as an input and
reading the port data register. See Table 16-2.
BYTE 1 BYTE 3
MISO/MOSI
BYTE 2
MASTER SS
SLAVE SS
CPHA = 0
SLAVE SS
CPHA = 1