Datasheet

Timer Interface Module (TIM2)
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
288 Freescale Semiconductor
function, and TIM2 channel 3 status and control register (T2SC3) is unused. While the MS2B bit is set,
the channel 3 pin, T2CH3, is available as a general-purpose I/O pin.
Channels 4 and 5 can be linked to form a buffered PWM channel whose output appears on the T2CH4
pin. The TIM2 channel registers of the linked pair alternately control the pulse width of the output.
Setting the MS4B bit in TIM2 channel 4 status and control register (T2SC4) links channel 4 and channel 5.
The TIM2 channel 4 registers initially control the pulse width on the T2CH4
pin. Writing to the TIM2
channel 5 registers enables the TIM2 channel 5 registers to synchronously control the pulse width at the
beginning of the next PWM period. At each subsequent overflow, the TIM2 channel registers (4 or 5) that
control the pulse width are the ones written to last. T2SC4 controls and monitors the buffered PWM
function, and TIM2 channel 5 status and control register (T2SC5) is unused. While the MS4B bit is set,
the channel 5 pin, T2CH5, is available as a general-purpose I/O pin.
NOTE
In buffered PWM signal generation, do not write pulse width values to the
currently active channel registers. User software should track the currently
active channel to prevent writing a new value to the active channel. Writing
to the active channel registers is the same as generating unbuffered PWM
signals.
19.3.4.3 PWM Initialization
To ensure correct operation when generating unbuffered or buffered PWM signals, use the following
initialization procedure:
1. In the TIM2 status and control register (T2SC):
a. Stop the TIM2 counter by setting the TIM2 stop bit, TSTOP.
b. Reset the TIM2 counter and prescaler by setting the TIM2 reset bit, TRST.
2. In the TIM2 counter modulo registers (T2MODH:T2MODL), write the value for the required PWM
period.
3. In the TIM2 channel x registers (T2CHxH:T2CHxL), write the value for the required pulse width.
4. In TIM2 channel x status and control register (T2SCx):
a. Write 0:1 (for unbuffered output compare or PWM signals) or 1:0 (for buffered output compare
or PWM signals) to the mode select bits, MSxB:MSxA. (See Table 19-2.)
b. Write 1 to the toggle-on-overflow bit, TOVx.
c. Write 1:0 (polarity 1 — to clear output on compare) or 1:1 (polarity 0 — to set output on
compare) to the edge/level select bits, ELSxB:ELSxA. The output action on compare must
force the output to the complement of the pulse width level. (See Table 19-2.)
NOTE
In PWM signal generation, do not program the PWM channel to toggle on
output compare. Toggling on output compare prevents reliable 0% duty
cycle generation and removes the ability of the channel to self-correct in the
event of software error or noise. Toggling on output compare can also
cause incorrect PWM signal generation when changing the PWM pulse
width to a new, much larger value.
5. In the TIM2 status control register (T2SC), clear the TIM2 stop bit, TSTOP.