Datasheet

System Integration Module (SIM)
Exception Control
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Technical Data
Freescale Semiconductor System Integration Module (SIM) 109
8.6.2.1 Interrupt Status Register 1
IF6–IF1 — Interrupt Flags 1–6
These flags indicate the presence of interrupt requests from the
sources shown in Table 8-4.
1 = Interrupt request present
0 = No interrupt request present
Bit 0 and Bit 1 — Always read 0
8.6.3 Reset
All reset sources always have equal and highest priority and cannot be
arbitrated.
8.6.4 Break Interrupts
The break module can stop normal program flow at a software-
programmable break point by asserting its break interrupt output. (See
Section 17. Break Module (BREAK).) The SIM puts the CPU into the
break state by forcing it to the SWI vector location. Refer to the break
interrupt subsection of each module to see how each module is affected
by the break state.
Address: $FE04
Bit 7654321Bit 0
Read: IF6 IF5 IF4 IF3 IF2 IF1 0 0
Write:RRRRRRRR
Reset:00000000
R=Reserved
Figure 8-12. Interrupt Status Register 1 (INT1)