Datasheet

System Integration Module (SIM)
Low-Power Modes
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Technical Data
Freescale Semiconductor System Integration Module (SIM) 111
Wait mode can also be exited by a reset or break. A break interrupt
during wait mode sets the SIM break stop/wait bit, SBSW, in the break
status register (BSR). If the COP disable bit, COPD, in the mask option
register is logic 0, then the computer operating properly module (COP)
is enabled and remains active in wait mode.
Figure 8-13. Wait Mode Entry Timing
Figure 8-14 and Figure 8-15 show the timing for WAIT recovery.
Figure 8-14. Wait Recovery from Interrupt or Break
Figure 8-15. Wait Recovery from Internal Reset
WAIT ADDR + 1 SAME SAMEIAB
IDB
PREVIOUS DATA NEXT OPCODE SAME
WAIT ADDR
SAME
R/W
NOTE: Previous data can be operand data or the WAIT opcode, depending on the
last instruction.
$6E0C$6E0B $00FF $00FE $00FD $00FC
$A6 $A6 $01 $0B $6E$A6
IAB
IDB
EXITSTOPWAIT
NOTE: EXITSTOPWAIT = RST
pin or CPU interrupt or break interrupt
IAB
IDB
RST
$A6 $A6
$6E0B
RST VCT H RST VCT L
$A6
OSCXCLK
32
CYCLES
32
CYCLES