Datasheet

Monitor ROM (MON)
Functional Description
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Technical Data
Freescale Semiconductor Monitor ROM (MON) 165
Figure 10-1. Monitor Mode Circuit
+
+
+
+
10MΩ
MC145407
MC74LCX125
HC908JB8
RST
IRQ
OSC1
OSC2
V
SS
PTA0
3.3V
10 kΩ
10k Ω
6
5
2
4
3
1
DB-25
2
3
7
20
18
17
19
16
15
3.3V
V
DD
20 pF
20 pF
10 µF
10 µF10 µF
10 µF
1
2
4
7
14
3
0.1 µF
6MHz
56
PTA1
V
DD
0.1 µF
V
DD
PTA2
3.3V
10 kΩ
PTA3
3.3V
10 kΩ
10 kΩ
SW1
A
B
V
DD
+ V
HI
SW2
E
F
(SEE NOTE 2)
NOTES:
1. Affects high voltage entry to monitor mode only (SW2 at position C):
SW1: Position A — Bus clock = f
XCLK
÷ 2
SW1: Position B — Bus clock = f
XCLK
2. SW2: Position C — High-voltage entry to monitor mode.
SW2: Position D — Low-voltage entry to monitor mode (with blank reset vector).
See Section 18 for IRQ voltage level requirements.
3. SW3: Position E — OSC1 directly driven by external oscillator.
SW3: Position F — OSC1 driven by crystal oscillator circuit.
10k Ω
V
DD
V
DD
(SEE NOTE 3)
(SEE NOTE 1)
E
F
C
D
6MHz
SW3
f
XCLK
V
REG
4.7 µF 0.1 µF
+