Datasheet

Timer Interface Module (TIM)
Technical Data MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
196 Timer Interface Module (TIM) Freescale Semiconductor
When ELSxB:ELSxA = 0:0, this read/write bit selects the initial output
level of the TCHx pin. (See Table 11-3.) Reset clears the MSxA bit.
1 = Initial output level low
0 = Initial output level high
NOTE: Before changing a channel function by writing to the MSxB or MSxA bit,
set the TSTOP and TRST bits in the TIM status and control register
(TSC).
ELSxB and ELSxA — Edge/Level Select Bits
When channel x is an input capture channel, these read/write bits
control the active edge-sensing logic on channel x.
When channel x is an output compare channel, ELSxB and ELSxA
control the channel x output behavior when an output compare
occurs.
When ELSxB and ELSxA are both clear, channel x is not connected
to port E, and pin PTEx/TCHx is available as a general-purpose I/O
pin. Table 11-3 shows how ELSxB and ELSxA work. Reset clears the
ELSxB and ELSxA bits.
Table 11-3. Mode, Edge, and Level Selection
MSxB MSxA ELSxB ELSxA Mode Configuration
X000
Output
Preset
Pin under port control;
initial output level high
X100
Pin under port control;
initial output level low
0001
Input
Capture
Capture on rising edge only
0010 Capture on falling edge only
0011 Capture on rising or falling edge
0101
Output
Compare
or PWM
Toggle output on compare
0110 Clear output on compare
0111 Set output on compare
1X01Buffered
Output
Compare or
Buffered
PWM
Toggle output on compare
1 X 1 0 Clear output on compare
1 X 1 1 Set output on compare