Datasheet

Input/Output Ports (I/O)
Technical Data MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
204 Input/Output Ports (I/O) Freescale Semiconductor
When bit DDRAx is a logic 1, reading address $0000 reads the PTAx
data latch. When bit DDRAx is a logic 0, reading address $0000 reads
the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 12-2 summarizes
the operation of the port A pins.
12.4 Port B
Port B is an 8-bit general-purpose bidirectional I/O port with software
configurable pullups.
12.4.1 Port B Data Register
The port B data register contains a data latch for each of the eight port B
pins.
NOTE: PTB7–PTB0 are not available in the 20-pin PDIP, 20-pin SOIC, and
28-pin SOIC packages.
Table 12-2. Port A Pin Functions
DDRA
Bit
PTA Bit I/O Pin Mode
Accesses
to DDRA
Accesses to PTA
Read/Write Read Write
0
X
(1)
NOTES:
1. X = don’t care.
Input, Hi-Z
(2)
2. Hi-Z = high impedance.
DDRA[7:0] Pin
PTA[7:0]
(3)
3. Writing affects data register, but does not affect input.
1 X Output DDRA[7:0] PTA[7:0] PTA[7:0]
Address: $0001
Bit 7654321Bit 0
Read:
PTB7 PTB6 PTB5 PTB4 PTB3 PTB2 PTB1 PTB0
Write:
Reset: Unaffected by reset
Additional
Function:
Optional
pullup
Optional
pullup
Optional
pullup
Optional
pullup
Optional
pullup
Optional
pullup
Optional
pullup
Optional
pullup
Figure 12-5. Port B Data Register (PTB)