Datasheet

Input/Output Ports (I/O)
Port B
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Technical Data
Freescale Semiconductor Input/Output Ports (I/O) 205
PTB[7:0] — Port B Data Bits
These read/write bits are software-programmable. Data direction of
each port B pin is under the control of the corresponding bit in data
direction register B. Reset has no effect on port B data.
The port B pullup enable bit, PBP, in the port option control register
(POCR) enables pullups on port B pins if the respective pin is
configured as an input. (See 12.8 Port Options.)
12.4.2 Data Direction Register B
Data direction register B determines whether each port B pin is an input
or an output. Writing a logic 1 to a DDRB bit enables the output buffer for
the corresponding port B pin; a logic 0 disables the output buffer.
DDRB[7:0] — Data Direction Register B Bits
These read/write bits control port B data direction. Reset clears
DDRB[7:0], configuring all port B pins as inputs.
1 = Corresponding port B pin configured as output
0 = Corresponding port B pin configured as input
NOTE: Avoid glitches on port B pins by writing to the port B data register before
changing data direction register B bits from 0 to 1.
NOTE: For those devices packaged in a 20-pin PDIP, 20-pin SOIC, and 28-pin
SOIC package, PTB7–PTB0 are not connected. DDRB7–DDRB0
should be set to a 1 to configure PTB7–PTB0 as outputs.
Figure 12-7 shows the port B I/O logic.
Address: $0005
Bit 7654321Bit 0
Read:
DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0
Write:
Reset:
00000000
Figure 12-6. Data Direction Register B (DDRB)