Datasheet

Computer Operating Properly (COP)
COP Control Register
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Technical Data
Freescale Semiconductor Computer Operating Properly (COP) 241
COPRS — COP Rate Select Bit
COPRS selects the COP timeout period. Reset clears COPRS.
1 = COP timeout period is (2
13
– 2
4
) × OSCXOUT cycles
0 = COP timeout period is (2
18
– 2
4
) × OSCXOUT cycles
COPD — COP Disable Bit
COPD disables the COP module.
1 = COP module disabled
0 = COP module enabled
15.5 COP Control Register
The COP control register is located at address $FFFF and overlaps the
reset vector. Writing any value to $FFFF clears the COP counter and
starts a new timeout period. Reading location $FFFF returns the low
byte of the reset vector.
15.6 Interrupts
The COP does not generate CPU interrupt requests.
15.7 Monitor Mode
The COP is disabled in monitor mode when V
DD
+ V
HI
is present on the
IRQ pin or on the RST pin.
Address: $FFFF
Bit 7654321Bit 0
Read: Low byte of reset vector
Write: Clear COP counter
Reset: Unaffected by reset
Figure 15-3. COP Control Register (COPCTL)