Datasheet

MC68HC08JB8
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Technical Data
Freescale Semiconductor MC68HC08JB8 275
A.7.2 Memory Characteristics
A.8 MC68HC08JB8 Order Numbers
These part numbers are generic numbers only. To place an order, ROM
code must be submitted to the ROM Processing Center (RPC).
NOTES:
1. V
DD
= 4.0 to 5.5 Vdc, V
SS
= 0 Vdc, T
A
= T
L
to T
H
, unless otherwise noted.
2. Typical values reflect average measurements at midpoint of voltage range, 25 °C only.
3. Run (operating) I
DD
measured using external square wave clock source (f
XCLK
= 6 MHz). All inputs 0.2 V from rail. No dc
loads. Less than 100 pF on all outputs. C
L
= 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly
affects run I
DD
. Measured with all modules enabled.
4. Wait I
DD
measured using external square wave clock source (f
XCLK
= 6 MHz); all inputs 0.2 V from rail; no dc loads; less
than 100 pF on all outputs. C
L
= 20 pF on OSC2; 15 kΩ ± 5% termination resistors on D+ and D– pins; all ports configured
as inputs; OSC2 capacitance linearly affects wait I
DD
5. STOP I
DD
measured with USB in suspend mode; OSC1 grounded; transceiver pullup resistor of 1.5 kΩ ± 5% between V
REG
and D– pins and 15 kΩ ± 5% termination resistor on D+ pin; no port pins sourcing current.
6. Maximum is highest voltage that POR is guaranteed.
7. If minimum V
REG
is not reached before the internal POR reset is released, RST must be driven low externally until minimum
V
REG
is reached.
Characteristic Symbol Min Max Unit
RAM data retention voltage
V
RDR
1.3 — V
Notes:
Since MC68HC08JB8 is a ROM device, FLASH memory electrical characteristics do not apply.
Table A-2. MC68HC08JB8 Order Numbers
MC Order Number Package
Operating
Temperature Range
MC68HC08JB8JP 20-pin PDIP 0 to +70 °C
MC68HC08JB8JDW 20-pin SOIC 0 to +70 °C
MC68HC08JB8ADW 28-pin SOIC 0 to +70 °C
MC68HC08JB8FB 44-pin QFP 0 to +70 °C