Datasheet

General Description
Pin Assignments
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Technical Data
Freescale Semiconductor General Description 33
Figure 1-3. 28-Pin SOIC Pin Assignments
Figure 1-4. 20-Pin PDIP and SOIC Pin Assignments
NOTE: In 20-pin package, the PTD0 and PTD1 internal pads are bonded
together to PTD0/1 pin.
1
2
3
4
5
6
7
28
27
26
25
24
23
22
21
20
19
18
12
13
14
17
16
15
8
9
10
11
OSC1
IRQ
PTA0/KBA0
RST
PTA1/KBA1
PTA2/KBA2
PTA3/KBA3
PTE0/TCLK
PTE2/TCH1
PTA4/KBA4
PTA5/KBA5
PTA6/KBA6
PTA7/KBA7
PTD5
PTD6
OSC2
V
REG
V
DD
PTD0
PTD1
PTD2
PTD3
PTD4
PTE1/TCH0
PTE3/D+
PTE4/D–
PTC0
V
SS
Pins not available on 28-pin package:
PTB0
PTB1 PTC1
PTB2 PTC2
PTB3 PTC3
PTB4 PTC4
PTB5 PTC5
PTB6 PTC6
PTB7 PTC7 PTD7
Internal pads are unconnected.
1
2
3
4
5
6
7
20
19
18
17
16
15
14
13
12
11
8
9
10
OSC1
PTA0/KBA0
RST
PTA1/KBA1
PTA2/KBA2
PTA3/KBA3
PTA4/KBA4
PTA5/KBA5
PTA6/KBA6
PTA7/KBA7
IRQ
OSC2
V
REG
V
DD
PTD0/1
PTE1/TCH0
PTE3/D+
PTE4/D–
PTC0
V
SS
PTD0/1 pin: PTD0 and PTD1 internal pads are
bonded together to PTD0/1 pin.
Pins not available on 20-pin package:
PTB0
PTE0/TCLK
PTB1 PTC1
PTB2 PTC2 PTD2 PTE2/TCH1
PTB3 PTC3 PTD3
PTB4 PTC4 PTD4
PTB5 PTC5 PTD5
PTB6 PTC6 PTD6
PTB7 PTC7 PTD7
Internal pads are unconnected.