Datasheet

Memory Map
Monitor ROM
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Technical Data
Freescale Semiconductor Memory Map 43
$000A
TIM Status and Control
Register
(TSC)
Read: TOF
TOIE TSTOP
00
PS2 PS1 PS0
Write: 0 TRST
Reset:00100000
$000B Unimplemented
Read:
Write:
$000C
TIM Counter Register
High
(TCNTH)
Read: Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8
Write:
Reset:00000000
$000D
TIM Counter Register
Low
(TCNTL)
Read: Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Write:
Reset:00000000
$000E
TIM Counter Modulo
Register High
(TMODH)
Read:
Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8
Write:
Reset:11111111
$000F
TIM Counter Modulo
Register Low
(TMODL)
Read:
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Write:
Reset:11111111
$0010
TIM Channel 0 Status and
Control Register
(TSC0)
Read: CH0F
CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX
Write: 0
Reset:00000000
$0011
TIM Channel 0
Register High
(TCH0H)
Read:
Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8
Write:
Reset: Indeterminate after reset
$0012
TIM Channel 0
Register Low
(TCH0L)
Read:
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Write:
Reset: Indeterminate after reset
$0013
TIM Channel 1 Status and
Control Register
(TSC1)
Read: CH1F
CH1IE
0
MS1A ELS1B ELS1A TOV1 CH1MAX
Write: 0
Reset:00000000
Addr.Register Name Bit 7654321Bit 0
= Unimplemented R = Reserved U = Unaffected by reset
Figure 2-2. Control, Status, and Data Registers (Sheet 2 of 8)