MC68HC908JB8 MC68HC08JB8 MC68HC08JT8 Technical Data M68HC08 Microcontrollers MC68HC908JB8/D Rev. 2.3 9/2005 freescale.
MC68HC908JB8 MC68HC08JB8 MC68HC08JT8 Technical Data To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location.
Revision History Revision History Date Revision Level September 2005 2.3 Added Pb-free parts. August 2005 2.2 Updated to meet Freescale identity guidelines. Page Number(s) Description 267, 284 Throughout 4.9 ROM-Resident Routines — Removed block erase references for ROM-resident routines. December 2003 61 9.8.8 USB Control Register 3 — Clarified bit descriptions for OSTALL0 and ISTALL0. 149, 150 9.8.11 USB Status Register 1 — Clarified bit descriptions for TXACK, TXNAK, and TXSTL.
Technical Data — MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 List of Sections Section 1. General Description . . . . . . . . . . . . . . . . . . . . 27 Section 2. Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Section 3. Random-Access Memory (RAM) . . . . . . . . . . 51 Section 4. FLASH Memory . . . . . . . . . . . . . . . . . . . . . . . . 53 Section 5. Configuration Register (CONFIG) . . . . . . . . . 65 Section 6. Central Processor Unit (CPU) . . . . . . . . . . . . 69 Section 7.
List of Sections Technical Data 6 MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.
Technical Data — MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 Table of Contents Section 1. General Description 1.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 1.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 1.4 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.
Table of Contents Section 3. Random-Access Memory (RAM) 3.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 3.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Section 4. FLASH Memory 4.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 4.2 Introduction . . . . . . . . .
Table of Contents Section 6. Central Processor Unit (CPU) 6.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 6.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 6.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 6.4 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 6.4.1 Accumulator . . . . . . . . . . . . . . . . . .
Table of Contents Section 8. System Integration Module (SIM) 8.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 8.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 8.3 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . . 96 8.3.1 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 8.3.2 Clock Startup from POR or LVI Reset . . . . . . . . . . . . . . .
Table of Contents 8.8.1 8.8.2 8.8.3 Break Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Reset Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Break Flag Control Register . . . . . . . . . . . . . . . . . . . . . . .116 Section 9. Universal Serial Bus Module (USB) 9.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 9.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table of Contents 9.8 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 9.8.1 USB Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 9.8.2 USB Interrupt Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . 139 9.8.3 USB Interrupt Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 141 9.8.4 USB Interrupt Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . 144 9.8.5 USB Control Register 0 . . . . . . . . . .
Table of Contents 10.4.6 10.5 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Section 11. Timer Interface Module (TIM) 11.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177 11.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 11.3 Features . . . . . . . . . . . . . . . . . . .
Table of Contents Section 12. Input/Output Ports (I/O) 12.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199 12.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 12.3 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 12.3.1 Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 12.3.2 Data Direction Register A. . . . . . . . . . . . . . .
Table of Contents Section 14. Keyboard Interrupt Module (KBI) 14.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227 14.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 14.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 14.4 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 14.5 Functional Description . . . . . . . . . . . .
Table of Contents 15.7 Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .241 15.8 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 15.8.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .242 15.8.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .242 15.9 COP Module During Break Mode . . . . . . . . . . . . . . . . . . . . . . 242 Section 16.
Table of Contents Section 18. Electrical Specifications 18.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .253 18.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 18.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . 254 18.4 Functional Operating Range. . . . . . . . . . . . . . . . . . . . . . . . . . 255 18.5 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . .
Table of Contents Appendix A. MC68HC08JB8 A.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .269 A.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 A.3 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 A.4 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 A.5 Reserved Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Technical Data — MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 List of Figures Figure Title 1-1 1-2 1-3 1-4 1-5 1-6 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 44-Pin QFP Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . 32 28-pin SOIC Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . 33 20-pin PDIP and SOIC Pin Assignments . . . . . . . . . . . . . . . . . 33 Power Supply Bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . .
List of Figures Figure Technical Data 20 Title Page 8-4 8-5 8-6 8-7 8-8 8-9 8-10 8-11 8-12 8-13 8-14 8-15 8-16 8-17 8-18 8-19 8-20 External Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 Internal Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Sources of Internal Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 POR Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Interrupt Processing . .
List of Figures Figure Title Page 9-19 9-20 9-21 9-22 9-23 9-24 9-25 9-26 9-27 9-28 9-29 9-30 9-31 9-32 USB Control Register 0 (UCR0) . . . . . . . . . . . . . . . . . . . . . . . 145 USB Control Register 1 (UCR1) . . . . . . . . . . . . . . . . . . . . . . . 146 USB Control Register 2 (UCR2) . . . . . . . . . . . . . . . . . . . . . . . 147 USB Control Register 3 (UCR3) . . . . . . . . . . . . . . . . . . . . . . . 149 USB Control Register 4 (UCR4) . . . . . . . . . . . . . . . . . . . . . . .
List of Figures 12-4 12-5 12-6 12-7 12-8 12-9 12-10 12-11 12-12 12-13 12-14 12-15 12-16 12-17 Port A I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 Port B Data Register (PTB) . . . . . . . . . . . . . . . . . . . . . . . . . . 204 Data Direction Register B (DDRB) . . . . . . . . . . . . . . . . . . . . . 205 Port B I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 Port C Data Register (PTC) . . . . . . . . . . . . . . . . . . . . . .
List of Figures Figure Title 19-1 19-2 19-3 19-4 44-Pin QFP (Case #824E) . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 28-Pin SOIC (Case #751F). . . . . . . . . . . . . . . . . . . . . . . . . . .265 20-Pin PDIP (Case #738) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 20-Pin SOIC (Case #751D) . . . . . . . . . . . . . . . . . . . . . . . . . . 266 A-1 A-2 MC68HC08JB8 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . 271 MC68HC08JB8 Memory Map. . . . . . . . . . . .
List of Figures Technical Data 24 MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.
Technical Data — MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 List of Tables Table Title 1-1 Summary of Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2-1 Vector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 4-1 4-2 4-3 4-4 4-5 ROM-Resident Routines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 ROM-Resident Routine Variables. . . . . . . . . . . . . . . . . . . . . . . 62 ERASE Routine . . . . . . . . . . . . . . . . . . . . . . .
List of Tables 11-1 TIM Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . 178 11-2 Prescaler Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 11-3 Mode, Edge, and Level Selection . . . . . . . . . . . . . . . . . . . . . . 196 12-1 12-2 12-3 12-4 12-5 12-6 Port Control Register Bits Summary. . . . . . . . . . . . . . . . . . . .201 Port A Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 Port B Pin Functions . . . . . . .
Technical Data — MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 Section 1. General Description 1.1 Contents 1.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 1.4 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.5 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 1.5.
General Description 1.3 Features Features of the MC68HC908JB8 include: • High-performance M68HC08 architecture • Fully upward-compatible object code with M6805, M146805, and M68HC05 Families • 3-MHz internal bus frequency • 8,192 bytes of on-chip FLASH memory • 256 bytes of on-chip random-access memory (RAM) • FLASH program memory security1 • On-chip programming firmware for use with host PC computer • Up to 37 general-purpose 3.
General Description Features • System protection features: – Optional computer operating properly (COP) reset – Optional low-voltage detection with reset – Illegal opcode detection with reset – Illegal address detection with reset • Low-power design (fully static with stop and wait modes) • Master reset pin with internal pullup and power-on reset • External interrupt pin with programmable internal pullup (IRQ) • 44-pin quad flat pack (QFP), 28-pin small outline integrated circuit package (SOIC), 2
General Description Features of the CPU08 include the following: • Enhanced HC05 programming model • Extensive loop control functions • 16 addressing modes (eight more than the HC05) • 16-bit index register and stack pointer • Memory-to-memory data transfers • Fast 8 × 8 multiply instruction • Fast 16/8 divide instruction • Binary-coded decimal (BCD) instructions • Optimization for controller applications • Efficient C language support 1.
PTA DDRB PTB PTB7–PTB0 (3) PTC PTC7–PTC0 (3) PTD PTD7–PTD6 (4) PTD5–PTD2 (4) (5) DDRA PTA7/KBA7 (3) : PTA0/KBA0 (3) DDRC CPU REGISTERS ARITHMETIC/LOGIC UNIT (ALU) KEYBOARD INTERRUPT MODULE CONTROL AND STATUS REGISTERS — 64 BYTES TIMER INTERFACE MODULE USER FLASH MEMORY — 8,192 BYTES USER RAM — 256 BYTES BREAK MODULE MONITOR ROM — 976 BYTES OSC1 OSC2 OSCILLATOR LOW VOLTAGE INHIBIT MODULE DDRD USER FLASH VECTORS — 16 BYTES PTD1–PTD0 (4) (6) POWER-ON RESET MODULE PTE4/D– (3) (4) (5) (1)
General Description OSC2 OSC1 VSS PTB3 PTB4 PTB5 PTB6 PTB7 RST PTA0/KBA0 PTA1/KBA1 44 43 42 41 40 39 38 37 36 35 34 1.
General Description Pin Assignments VSS 1 28 RST OSC1 2 27 PTA0/KBA0 OSC2 3 26 PTA1/KBA1 VREG 4 25 PTA2/KBA2 VDD 5 24 PTA3/KBA3 PTD0 6 23 PTE0/TCLK PTB0 Pins not available on 28-pin package: PTD1 7 22 PTE2/TCH1 PTD2 8 21 PTA4/KBA4 PTB1 PTC1 PTD3 9 20 PTA5/KBA5 PTB2 PTC2 PTD4 10 19 PTA6/KBA6 PTB3 PTC3 PTB4 PTC4 PTB5 PTC5 PTB6 PTC6 PTB7 PTC7 PTE1/TCH0 11 18 PTA7/KBA7 PTE3/D+ 12 17 PTD5 PTE4/D– 13 16 PTD6 PTC0 14 15 IRQ PTD7 Internal pad
General Description 1.5.1 Power Supply Pins (VDD, VSS) VDD and VSS are the power supply and ground pins. The MCU operates from a single power supply. Fast signal transitions on MCU pins place high, short-duration current demands on the power supply. To prevent noise problems, take special care to provide power supply bypassing at the MCU as Figure 1-5 shows. Place the bypass capacitors as close to the MCU power pins as possible. Use high-frequency-response ceramic capacitors for CBYPASS.
General Description Pin Assignments VREG MCU VSS CREGBYPASS 0.1 µF + CREGBULK > 4.7 µF VREG Figure 1-6. Regulator Supply Capacitor Configuration 1.5.3 Oscillator Pins (OSC1 and OSC2) The OSC1 and OSC2 pins are the connections for the on-chip oscillator circuit. 1.5.4 External Reset Pin (RST) A logic zero on the RST pin forces the MCU to a known start-up state. RST is bidirectional, allowing a reset of the entire system. It is driven low when any internal reset source is asserted.
General Description 1.5.6 Port A Input/Output (I/O) Pins (PTA7/KBA7–PTA0/KBA0) PTA7/KBA7–PTA0/KBA0 are general-purpose bidirectional I/O port pins. (See Section 12. Input/Output Ports (I/O).) Each pin contains a software configurable pullup device to VREG when the pin is configured as an input. (See 12.8 Port Options.) Each pin can also be programmed as an external keyboard interrupt pin. (See Section 14. Keyboard Interrupt Module (KBI).) 1.5.
General Description Pin Assignments When the USB module is disabled, the PTE4 and PTE3 pins are general-purpose bidirectional I/O port pins with 10mA sink capability. Each pin is open-drain when configured as an output; and each pin contains a software configurable 5kΩ pullup to VDD when configured as an input. The PTE4 pin can also be enabled to trigger the IRQ interrupt. When the USB module is enabled, the PTE4/D– and PTE3/D+ pins become the USB module D– and D+ pins.
General Description Table 1-1. Summary of Pin Functions PIN NAME PIN DESCRIPTION IN/OUT VOLTAGE LEVEL IN/OUT VREG IN VREG 8-bit general-purpose I/O port; open-drain when configured as output. IN OUT VREG VREG or VDD PTD0–PTD1 have configurable 25mA sink for infrared LED. OUT VREG or VDD PTD2–PTD5 have configurable 10mA sink for LED. OUT VREG or VDD PTE0–PTE2 are general-purpose I/O pins. IN/OUT VREG PTE0–PTE2 have programmable internal pullup to VREG when configured as input or output.
Technical Data — MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 Section 2. Memory Map 2.1 Contents 2.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.3 I/O Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.4 Monitor ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 2.2 Introduction The CPU08 can address 64 Kbytes of memory space.
Memory Map $0000 ↓ $003F I/O Registers 64 Bytes $0040 ↓ $013F RAM 256 Bytes $0140 ↓ $DBFF Unimplemented 56,000 Bytes $DC00 ↓ $FBFF FLASH 8,192 Bytes $FC00 ↓ $FDFF Monitor ROM 1 512 Bytes $FE00 Break Status Register (BSR) $FE01 Reset Status Register (RSR) $FE02 Reserved $FE03 Break Flag Control Register (BFCR) $FE04 Interrupt Status Register 1 (INT1) $FE05 Reserved $FE06 Reserved $FE07 Reserved $FE08 FLASH Control Register (FLCR) $FE09 FLASH Block Protect Register (FLBPR) $FE0A
Memory Map I/O Section 2.3 I/O Section Addresses $0000–$003F, shown in Figure 2-2, contain most of the control, status, and data registers.
Memory Map Addr.
Memory Map Monitor ROM Addr.
Memory Map Addr.
Memory Map Monitor ROM Addr. $001E $001F Register Name Bit 7 6 5 4 3 2 Read: IRQ Status and Control Register Write: (ISCR) Reset: 0 0 0 0 IRQF 0 0 0 Read: Configuration Register Write: (CONFIG)† Reset: 0 0 0 0 ACK 1 Bit 0 IMASK MODE 0 0 0 0 0 0 URSTD LVID SSREC COPRS STOP COPD 0 0 0 0 0 0 † One-time writable register after each reset. URSTD and LVID bits are reset by POR or LVI reset only.
Memory Map Addr.
Memory Map Monitor ROM Addr.
Memory Map Addr.
Memory Map Monitor ROM Addr.
Memory Map Table 2-1 is a list of vector locations. Table 2-1.
Technical Data — MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 Section 3. Random-Access Memory (RAM) 3.1 Contents 3.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 3.2 Introduction This section describes the 256 bytes of RAM. 3.3 Functional Description Addresses $0040–$013F are RAM locations. The location of the stack RAM is programmable.
Random-Access Memory (RAM) During a subroutine call, the CPU uses two bytes of the stack to store the return address. The stack pointer decrements during pushes and increments during pulls. NOTE: Technical Data 52 Be careful when using nested subroutines. The CPU may overwrite data in the RAM during a subroutine or during the interrupt stacking operation. MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.
Technical Data — MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 Section 4. FLASH Memory 4.1 Contents 4.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 4.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 4.4 FLASH Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4.5 FLASH Block Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . 56 4.6 FLASH Mass Erase Operation . . . . . . .
FLASH Memory Addr. $FE08 $FE09 Register Name Bit 7 6 5 4 FLASH Control Register Read: (FLCR) Write: 0 0 0 0 Reset: 0 0 0 BPR7 BPR6 0 0 FLASH Block Protect Read: Register (FLBPR) Write: Reset: 3 2 1 Bit 0 HVEN MASS ERASE PGM 0 0 0 0 0 BPR5 BPR4 BPR3 BPR2 BPR1 BPR0 0 0 0 0 0 0 Figure 4-1. FLASH Memory Register Summary 4.
FLASH Memory FLASH Control Register 4.4 FLASH Control Register The FLASH control register (FLCR) controls FLASH program and erase operations. Address: Read: $FE08 Bit 7 6 5 4 0 0 0 0 3 2 1 Bit 0 HVEN MASS ERASE PGM 0 0 0 0 Write: Reset: 0 0 0 0 Figure 4-2. FLASH Control Register (FLCR) HVEN — High Voltage Enable Bit This read/write bit enables high voltage from the charge pump to the memory for either program or erase operation.
FLASH Memory 4.5 FLASH Block Erase Operation Use the following procedure to erase a block of FLASH memory. A block consists of 512 consecutive bytes starting from addresses $X000, $X200, $X400, $X600, $X800, $XA00, $XC00 or $XE00. Any block within the 8,192 bytes user memory area ($DC00–$FBFF) can be erased alone. NOTE: The 16-byte user vectors, $FFF0–$FFFF, cannot be erased by the block erase operation because of security reasons. Mass erase is required to erase this block. 1.
FLASH Memory FLASH Mass Erase Operation 4.6 FLASH Mass Erase Operation Use the following procedure to erase the entire FLASH memory: 1. Set both the ERASE bit and the MASS bit in the FLASH control register. 2. Write any data to any FLASH address within the address range $FFE0–$FFFF. 3. Wait for a time, tnvs (5 µs). 4. Set the HVEN bit. 5. Wait for a time tme (2 ms). 6. Clear the ERASE bit. 7. Wait for a time, tnvh1 (100 µs). 8. Clear the HVEN bit. 9.
FLASH Memory 4.7 FLASH Program Operation Programming of the FLASH memory is done on a row basis. A row consists of 64 consecutive bytes starting from addresses $XX00, $XX40, $XX80 or $XXC0. The procedure for programming a row of the FLASH memory is outlined below: 1. Set the PGM bit. This configures the memory for program operation and enables the latching of address and data for programming. 2. Write any data to any FLASH address within the address range of the row to be programmed. 3.
FLASH Memory FLASH Program Operation 1 Algorithm for programming a row (64 bytes) of FLASH memory Set PGM bit 2 Write any data to any FLASH address within the row address range desired 3 Wait for a time, tnvs 4 Set HVEN bit 5 Wait for a time, tpgs 6 Write data to the FLASH address to be programmed 7 Wait for a time, tPROG Completed programming this row? Y N NOTE: The time between each FLASH address change (step 6 to step 6), or the time between the last FLASH address programmed to clearin
FLASH Memory 4.8 FLASH Protection Due to the ability of the on-board charge pump to erase and program the FLASH memory in the target application, provision is made to protect blocks of memory from unintentional erase or program operations due to system malfunction. This protection is done by use of a FLASH block protect register (FLBPR). The FLBPR determines the range of the FLASH memory which is to be protected.
FLASH Memory ROM-Resident Routines BPR0 is used only for BPR[7:0] = $FF, for no block protection. The resultant 16-bit address is used for specifying the start address of the FLASH memory for block protection. The FLASH is protected from this start address to the end of FLASH memory, at $FFFF. With this mechanism, the protect start address can be X000, X200, X400, X600, X800, XA00, XC00, or XE00 within the FLASH memory.
FLASH Memory 4.9.1 Variables The ROM-resident routines use three variables: CTRLBYT, CPUSPD and LADDR; and one data buffer. The minimum size of the data buffer is one byte and the maximum size is 64 bytes. CPUSPD must be set before calling the ERASE or PROGRAM routine, and should be set to four times the value of the CPU internal bus speed in MHz. For example: for CPU speed of 3MHz, CPUSPD should be set to 12. Table 4-2.
FLASH Memory ROM-Resident Routines 4.9.3 PROGRAM Routine The PROGRAM routine programs a range of addresses in FLASH memory, which does not have to be on page boundaries, either at the begin or end address. Table 4-4. PROGRAM Routine Routine PROGRAM Calling Address $FC09 Stack Use 7 Bytes Input CPUSPD — HX — LADDR — DATABUF — CPU speed FLASH start address to be programmed FLASH end address to be programmed Contains the data to be programmed 4.9.
FLASH Memory Technical Data 64 MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.
Technical Data — MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 Section 5. Configuration Register (CONFIG) 5.1 Contents 5.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 5.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 5.2 Introduction This section describes the configuration register (CONFIG).
Configuration Register (CONFIG) 5.3 Functional Description The configuration register is used in the initialization of various options. The configuration register can be written once after each reset. Bit-5 and bit-4 are cleared by a POR or LVI reset only. Bit-3 to bit-0 are cleared during any reset. Since the various options affect the operation of the MCU, it is recommended that this register be written immediately after reset. The configuration register is located at $001F.
Configuration Register (CONFIG) Functional Description NOTE: Exiting stop mode by pulling reset will result in the long stop recovery. If using an external crystal, do not set the SSREC bit. COPRS — COP Rate Select Bit COPD selects the COP timeout period. Reset clears COPRS. (See Section 15. Computer Operating Properly (COP).) 1 = COP timeout period = (213 – 24)×OSCXCLK cycles 0 = COP timeout period = (218 – 24)×OSCXCLK cycles STOP — STOP Instruction Enable Bit STOP enables the STOP instruction.
Configuration Register (CONFIG) Technical Data 68 MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.
Technical Data — MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 Section 6. Central Processor Unit (CPU) 6.1 Contents 6.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 6.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 6.4 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 6.4.1 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 6.4.
Central Processor Unit (CPU) 6.2 Introduction The M68HC08 CPU (central processor unit) is an enhanced and fully object-code-compatible version of the M68HC05 CPU. The CPU08 Reference Manual (Freescale document order number CPU08RM/AD) contains a description of the CPU instruction set, addressing modes, and architecture. 6.
Central Processor Unit (CPU) CPU Registers 6.4 CPU Registers Figure 6-1 shows the five CPU registers. CPU registers are not part of the memory map. 0 7 ACCUMULATOR (A) 0 15 H X INDEX REGISTER (H:X) 15 0 STACK POINTER (SP) 15 0 PROGRAM COUNTER (PC) 7 0 V 1 1 H I N Z C CONDITION CODE REGISTER (CCR) CARRY/BORROW FLAG ZERO FLAG NEGATIVE FLAG INTERRUPT MASK HALF-CARRY FLAG TWO’S COMPLEMENT OVERFLOW FLAG Figure 6-1. CPU Registers 6.4.
Central Processor Unit (CPU) 6.4.2 Index Register The 16-bit index register allows indexed addressing of a 64-Kbyte memory space. H is the upper byte of the index register, and X is the lower byte. H:X is the concatenated 16-bit index register. In the indexed addressing modes, the CPU uses the contents of the index register to determine the conditional address of the operand. The index register can serve also as a temporary data storage location.
Central Processor Unit (CPU) CPU Registers NOTE: The location of the stack is arbitrary and may be relocated anywhere in RAM. Moving the SP out of page 0 ($0000 to $00FF) frees direct address (page 0) space. For correct operation, the stack pointer must point only to RAM locations. 6.4.4 Program Counter The program counter is a 16-bit register that contains the address of the next instruction or operand to be fetched.
Central Processor Unit (CPU) 6.4.5 Condition Code Register The 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the instruction just executed. Bits 6 and 5 are set permanently to logic 1. The following paragraphs describe the functions of the condition code register. Bit 7 6 5 4 3 2 1 Bit 0 V 1 1 H I N Z C X 1 1 X 1 X X X Read: Write: Reset: X = Indeterminate Figure 6-6.
Central Processor Unit (CPU) CPU Registers I — Interrupt Mask When the interrupt mask is set, all maskable CPU interrupts are disabled. CPU interrupts are enabled when the interrupt mask is cleared. When a CPU interrupt occurs, the interrupt mask is set automatically after the CPU registers are saved on the stack, but before the interrupt vector is fetched.
Central Processor Unit (CPU) C — Carry/Borrow Flag The CPU sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. Some instructions — such as bit test and branch, shift, and rotate — also clear or set the carry/borrow flag. 1 = Carry out of bit 7 0 = No carry out of bit 7 6.5 Arithmetic/Logic Unit (ALU) The ALU performs the arithmetic and logic operations defined by the instruction set.
Central Processor Unit (CPU) CPU During Break Interrupts 6.6.2 Stop Mode The STOP instruction: • Clears the interrupt mask (I bit) in the condition code register, enabling external interrupts. After exit from stop mode by external interrupt, the I bit remains clear. After exit by reset, the I bit is set. • Disables the CPU clock After exiting stop mode, the CPU clock begins running after the oscillator stabilization delay. 6.
Central Processor Unit (CPU) 6.
Central Processor Unit (CPU) Instruction Set Summary Effect on CCR V H I N Z C BCC rel PC ← (PC) + 2 + rel ? (C) = 0 Branch if Carry Bit Clear Mn ← 0 Cycles Description Operand Operation Opcode Source Form Address Mode Table 6-1.
Central Processor Unit (CPU) Effect on CCR V H I N Z C Cycles Description Operand Operation Opcode Source Form Address Mode Table 6-1.
Central Processor Unit (CPU) Instruction Set Summary Effect on CCR V H I N Z C CLR opr CLRA CLRX CLRH CLR opr,X CLR ,X CLR opr,SP CMP #opr CMP opr CMP opr CMP opr,X CMP opr,X CMP ,X CMP opr,SP CMP opr,SP Clear Compare A with M COM opr COMA COMX COM opr,X COM ,X COM opr,SP Complement (One’s Complement) CPHX #opr CPHX opr Compare H:X with M CPX #opr CPX opr CPX opr CPX ,X CPX opr,X CPX opr,X CPX opr,SP CPX opr,SP Compare X with M DAA Decimal Adjust A M ← $00 A ← $00 X ← $00 H ← $00 M ← $00 M ← $0
Central Processor Unit (CPU) V H I N Z C EOR #opr EOR opr EOR opr EOR opr,X EOR opr,X EOR ,X EOR opr,SP EOR opr,SP INC opr INCA INCX INC opr,X INC ,X INC opr,SP JMP opr JMP opr JMP opr,X JMP opr,X JMP ,X JSR opr JSR opr JSR opr,X JSR opr,X JSR ,X LDHX #opr LDHX opr Load H:X from M LSL opr LSLA LSLX LSL opr,X LSL ,X LSL opr,SP Technical Data 82 ii dd hh ll ee ff ff M ← (M) + 1 A ← (A) + 1 X ← (X) + 1 M ← (M) + 1 M ← (M) + 1 M ← (M) + 1 DIR INH INH R – – R R – IX1 IX SP1 3C 4C 5C 6C 7C 9E6C dd PC ←
Central Processor Unit (CPU) Instruction Set Summary V H I N Z C LSR opr LSRA LSRX LSR opr,X LSR ,X LSR opr,SP Logical Shift Right DIR INH INH R – – 0 R R IX1 IX SP1 34 44 54 64 74 9E64 DD DIX+ 0 – – R R – IMD IX+D 4E 5E 6E 7E X:A ← (X) × (A) – 0 – – – 0 INH 42 M ← –(M) = $00 – (M) A ← –(A) = $00 – (A) X ← –(X) = $00 – (X) M ← –(M) = $00 – (M) M ← –(M) = $00 – (M) DIR INH INH R – – R R R IX1 IX SP1 30 40 50 60 70 9E60 0 C b7 MOV opr,opr MOV opr,X+ MOV #opr,opr MOV X+,opr Move MUL Unsigned
Central Processor Unit (CPU) V H I N Z C ROR opr RORA RORX ROR opr,X ROR ,X ROR opr,SP Rotate Right through Carry RSP Reset Stack Pointer RTI Return from Interrupt RTS Return from Subroutine dd Cycles Effect on CCR Description Operand Operation Opcode Source Form Address Mode Table 6-1.
Central Processor Unit (CPU) Instruction Set Summary Effect on CCR V H I N Z C SUB #opr SUB opr SUB opr SUB opr,X SUB opr,X SUB ,X SUB opr,SP SUB opr,SP Subtract A ← (A) – (M) ii dd hh ll ee ff ff Cycles Description Operand Operation Opcode Source Form Address Mode Table 6-1.
Central Processor Unit (CPU) V H I N Z C A C CCR dd dd rr DD DIR DIX+ ee ff EXT ff H H hh ll I ii IMD IMM INH IX IX+ IX+D IX1 IX1+ IX2 M N Accumulator Carry/borrow bit Condition code register Direct address of operand Direct address of operand and relative offset of branch instruction Direct to direct addressing mode Direct addressing mode Direct to indexed with post increment addressing mode High and low bytes of offset in indexed, 16-bit offset addressing Extended addressing mode Offset byte in indexed,
Central Processor Unit (CPU) MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Freescale Semiconductor Table 6-2.
Central Processor Unit (CPU) Technical Data 88 MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.
Technical Data — MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 Section 7. Oscillator (OSC) 7.1 Contents 7.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 7.3 Oscillator External Connections . . . . . . . . . . . . . . . . . . . . . . . .90 7.4 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 7.4.1 Crystal Amplifier Input Pin (OSC1). . . . . . . . . . . . . . . . . . . . 91 7.4.2 Crystal Amplifier Output Pin (OSC2) .
Oscillator (OSC) 7.3 Oscillator External Connections In its typical configuration, the oscillator requires five external components. The crystal oscillator is normally connected in a Pierce oscillator configuration, as shown in Figure 7-1. This figure shows only the logical representation of the internal components and may not represent actual circuitry.
Oscillator (OSC) I/O Signals The series resistor (RS) is included in the diagram to follow strict Pierce oscillator guidelines and may not be required for all ranges of operation, especially with high-frequency crystals. Refer to the crystal manufacturer’s data for more information. 7.4 I/O Signals The following paragraphs describe the oscillator input/output (I/O) signals. 7.4.1 Crystal Amplifier Input Pin (OSC1) The OSC1 pin is an input to the crystal oscillator amplifier. 7.4.
Oscillator (OSC) 7.4.5 Oscillator Out (OSCOUT) The clock driven to the SIM is OSCXCLK. This signal is driven to the SIM for generation of the bus clocks used by the CPU and other modules on the MCU. OSCOUT will be divided again in the SIM and results in the internal bus frequency being one forth of the OSCXCLK frequency or one half of the crystal frequency. 7.5 Low-Power Modes The WAIT and STOP instructions put the MCU in low-powerconsumption standby modes. 7.5.
Technical Data — MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 Section 8. System Integration Module (SIM) 8.1 Contents 8.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 8.3 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . . 96 8.3.1 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 8.3.2 Clock Startup from POR or LVI Reset . . . . . . . . . . . . . . . . . 97 8.3.3 Clocks in Stop Mode and Wait Mode . .
System Integration Module (SIM) 8.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 8.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110 8.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 8.8 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 8.8.1 Break Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 8.8.
System Integration Module (SIM) Introduction MODULE STOP MODULE WAIT CPU STOP (FROM CPU) CPU WAIT (FROM CPU) STOP/WAIT CONTROL SIMOSCEN (TO OSCILLATOR) SIM COUNTER COP CLOCK OSCXCLK (FROM CLOCK DOUBLER) OSCOUT (FROM CLOCK DOUBLER) ÷2 VDD INTERNAL PULL-UP RESET PIN LOGIC CLOCK CONTROL CLOCK GENERATORS POR CONTROL MASTER RESET CONTROL RESET PIN CONTROL SIM RESET STATUS REGISTER INTERNAL CLOCKS ILLEGAL OPCODE (FROM CPU) ILLEGAL ADDRESS (FROM ADDRESS MAP DECODERS) COP TIMEOUT (FROM COP MODULE) LVI
System Integration Module (SIM) Addr. $FE00 Register Name Break Status Register Read: (BSR) Write: Bit 7 6 5 4 3 2 R R R R R R Reset: 1 SBSW See note Bit 0 R 0 Note: Writing a logic 0 clears SBSW.
System Integration Module (SIM) Reset and System Initialization 8.3.1 Bus Timing In user mode, the internal bus frequency is the oscillator frequency divided by two. 8.3.2 Clock Startup from POR or LVI Reset When the power-on reset (POR) module or the low-voltage inhibit module generates a reset, the clocks to the CPU and peripherals are inactive and held in an inactive phase until after the 4096 OSCXCLK cycle POR timeout has completed. The RST pin is driven low by the SIM during this entire period.
System Integration Module (SIM) All of these resets produce the vector $FFFE–FFFF ($FEFE–FEFF in monitor mode) and assert the internal reset signal (IRST). IRST causes all registers to be returned to their default values and all modules to be returned to their reset states. An internal reset clears the SIM counter (see 8.5 SIM Counter), but an external reset does not. Each of the resets sets a corresponding bit in the reset status register (RSR). (See 8.8 SIM Registers.) 8.4.
System Integration Module (SIM) Reset and System Initialization 8.4.2 Active Resets from Internal Sources All internal reset sources actively pull the RST pin low for 32 OSCXCLK cycles to allow resetting of external peripherals. The internal reset signal IRST continues to be asserted for an additional 32 cycles. (See Figure 8-5.) An internal reset can be caused by an illegal address, illegal opcode, COP timeout, LVI, the USB module or POR. (See Figure 8-6 . Sources of Internal Reset.
System Integration Module (SIM) 8.4.2.1 Power-On Reset When power is first applied to the MCU, the power-on reset module (POR) generates a pulse to indicate that power-on has occurred. The external reset pin (RST) is held low while the SIM counter counts out 4096 OSCXCLK cycles. Sixty-four OSCXCLK cycles later, the CPU and memories are released from reset to allow the reset vector sequence to occur. At power-on, the following events occur: • A POR pulse is generated.
System Integration Module (SIM) Reset and System Initialization 8.4.2.2 Computer Operating Properly (COP) Reset An input to the SIM is reserved for the COP reset signal. The overflow of the COP counter causes an internal reset and sets the COP bit in the reset status register (RSR). The SIM actively pulls down the RST pin for all internal reset sources. To prevent a COP module timeout, write any value to location $FFFF.
System Integration Module (SIM) 8.4.2.5 Low-Voltage Inhibit (LVI) Reset The low-voltage inhibit module (LVI) asserts its output to the SIM when the VDD voltage falls to the LVI reset voltage, VTRIP. The LVI bit in the reset status register (RSR) is set, and the external reset pin (RST) is held low while the SIM counter counts out 4096 OSCXCLK cycles. Sixty-four OSCXCLK cycles later, the CPU is released from reset to allow the reset vector sequence to occur.
System Integration Module (SIM) SIM Counter Table 8-3.
System Integration Module (SIM) 8.5.2 SIM Counter During Stop Mode Recovery The SIM counter also is used for stop mode recovery. The STOP instruction clears the SIM counter. After an interrupt, break, or reset, the SIM senses the state of the short stop recovery bit, SSREC, in the configuration register (CONFIG). If the SSREC bit is a logic 1, then the stop recovery is reduced from the normal delay of 4096 OSCXCLK cycles down to 2048 OSCXCLK cycles.
System Integration Module (SIM) Exception Control FROM RESET BREAK INTERRUPT ? NO YES YES BITSET? SET? IIBIT NO IRQ INTERRUPT ? NO YES USB INTERRUPT ? NO YES OTHER INTERRUPTS ? NO YES STACK CPU REGISTERS SET I BIT LOAD PC WITH INTERRUPT VECTOR FETCH NEXT INSTRUCTION SWI INSTRUCTION ? YES NO RTI INSTRUCTION ? YES UNSTACK CPU REGISTERS NO EXECUTE INSTRUCTION Figure 8-8. Interrupt Processing MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.
System Integration Module (SIM) Interrupts are latched and arbitration is performed in the SIM at the start of interrupt processing. The arbitration result is a constant that the CPU uses to determine which vector to fetch. Once an interrupt is latched by the SIM, no other interrupt can take precedence, regardless of priority, until the latched interrupt is serviced or the I bit is cleared.
System Integration Module (SIM) Exception Control 8.6.1.1 Hardware Interrupts A hardware interrupt does not stop the current instruction. Processing of a hardware interrupt begins after completion of the current instruction. When the current instruction is complete, the SIM checks all pending hardware interrupts.
System Integration Module (SIM) 8.6.1.2 SWI Instruction The SWI instruction is a non-maskable instruction that causes an interrupt regardless of the state of the interrupt mask (I bit) in the condition code register. NOTE: A software interrupt pushes PC onto the stack. A software interrupt does not push PC–1, as a hardware interrupt does. 8.6.2 Interrupt Status Registers The flags in the interrupt status registers identify maskable interrupt sources.
System Integration Module (SIM) Exception Control 8.6.2.1 Interrupt Status Register 1 Address: $FE04 Bit 7 6 5 4 3 2 1 Bit 0 Read: IF6 IF5 IF4 IF3 IF2 IF1 0 0 Write: R R R R R R R R Reset: 0 0 0 0 0 0 0 0 R = Reserved Figure 8-12. Interrupt Status Register 1 (INT1) IF6–IF1 — Interrupt Flags 1–6 These flags indicate the presence of interrupt requests from the sources shown in Table 8-4.
System Integration Module (SIM) 8.6.5 Status Flag Protection in Break Mode The SIM controls whether status flags contained in other modules can be cleared during break mode. The user can select whether flags are protected from being cleared by properly initializing the break clear flag enable bit (BCFE) in the break flag control register (BFCR). Protecting flags in break mode ensures that set flags will not be cleared while in break mode.
System Integration Module (SIM) Low-Power Modes Wait mode can also be exited by a reset or break. A break interrupt during wait mode sets the SIM break stop/wait bit, SBSW, in the break status register (BSR). If the COP disable bit, COPD, in the mask option register is logic 0, then the computer operating properly module (COP) is enabled and remains active in wait mode.
System Integration Module (SIM) 8.7.2 Stop Mode In stop mode, the SIM counter is reset and the system clocks are disabled. An interrupt request from a module can cause an exit from stop mode. Stacking for interrupts begins after the selected stop recovery time has elapsed. Reset or break also causes an exit from stop mode. The SIM disables the oscillator signals (OSCOUT and OSCXCLK) in stop mode, stopping the CPU and peripherals.
System Integration Module (SIM) SIM Registers STOP RECOVERY PERIOD OSCXCLK INT/BREAK IAB STOP +1 STOP + 2 STOP + 2 SP SP – 1 SP – 2 SP – 3 Figure 8-17. Stop Mode Recovery from Interrupt or Break 8.8 SIM Registers The SIM has two break registers and one reset register. 8.8.1 Break Status Register The break status register contains a flag to indicate that a break caused an exit from stop or wait mode.
System Integration Module (SIM) SBSW can be read within the break state SWI routine. The user can modify the return address on the stack by subtracting one from it. The following code is an example of this. Writing 0 to the SBSW bit clears it. This code works if the H register has been pushed onto the stack in the break service routine software. This code should be executed at the end of the break service routine software.
System Integration Module (SIM) SIM Registers Address: Read: $FE01 Bit 7 6 5 4 3 2 1 Bit 0 POR PIN COP ILOP ILAD USB LVI 0 1 0 0 0 0 0 0 0 Write: POR: = Unimplemented Figure 8-19.
System Integration Module (SIM) 8.8.3 Break Flag Control Register The break control register contains a bit that enables software to clear status bits while the MCU is in a break state. Address: $FE03 Bit 7 6 5 4 3 2 1 Bit 0 BCFE R R R R R R R Read: Write: POR: 0 R = Reserved Figure 8-20. Break Flag Control Register (BFCR) BCFE — Break Clear Flag Enable Bit This read/write bit enables software to clear status bits by accessing status registers while the MCU is in a break state.
Technical Data — MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 Section 9. Universal Serial Bus Module (USB) 9.1 Contents 9.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 9.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 9.4 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 9.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124 9.5.
Universal Serial Bus Module (USB) 9.7.3 USB Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 9.8 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 9.8.1 USB Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 9.8.2 USB Interrupt Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . 139 9.8.3 USB Interrupt Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 141 9.8.
Universal Serial Bus Module (USB) Features 9.3 Features Features of the USB module include: • Full Universal Serial Bus Specification 1.1 low-speed functions • 1.5 Mbps data rate • On-chip 3.
Universal Serial Bus Module (USB) 9.4 Pin Name Conventions The USB share two I/O pins with two port E I/O pins. The full name of the USB I/O pin is listed in Table 9-1. The generic pin name appear in the text that follows. Table 9-1. USB Module Pin Name Conventions Addr.
Universal Serial Bus Module (USB) Pin Name Conventions Addr.
Universal Serial Bus Module (USB) Addr.
Universal Serial Bus Module (USB) Pin Name Conventions Addr.
Universal Serial Bus Module (USB) 9.5 Functional Description Figure 9-2 shows the block diagram of the USB module. The USB module manages communications between the host and the USB function. The module is partitioned into three functional blocks. These blocks consist of a dual-function transceiver, the USB control logic, and the endpoint registers. The blocks are further detailed later in this section (see 9.7 Hardware Description).
Universal Serial Bus Module (USB) Functional Description 9.5.1 USB Protocol Figure 9-3 shows the various transaction types supported by the USB module. The transactions are portrayed as error free. The effect of errors in the data flow are discussed later.
Universal Serial Bus Module (USB) Each USB transaction is comprised of a series of packets. The USB module supports the packet types shown in Figure 9-4. Token packets are generated by the USB host and decoded by the USB device. Data and handshake packets are both decoded and generated by the USB device, depending on the type of transaction.
Universal Serial Bus Module (USB) Functional Description The start of a packet (SOP) is signaled by the originating port by driving the D+ and D– lines from the idle state (also referred to as the J state) to the opposite logic level (also referred to as the K state). This switch in levels represents the first bit of the sync field. Figure 9-6 shows the data signaling and voltage levels for the start of packet and the sync pattern. VOH (min.) VSE (max) VSE (min.) VOL (min.
Universal Serial Bus Module (USB) 9.5.1.3 Address Field (ADDR) The address field is a 7-bit number that is used to select a particular USB device. This field is compared to the lower seven bits of the UADDR register to determine if a given transaction is targeting the MCU USB device. 9.5.1.4 Endpoint Field (ENDP) The endpoint field is a 4-bit number that is used to select a particular endpoint within a USB device. For the MCU, this will be a binary number between 0 and 2 inclusive.
Universal Serial Bus Module (USB) Functional Description LAST BIT OF PACKET EOP STROBE BUS DRIVEN TO IDLE STATE BUS FLOATS BUS IDLE VOH (min.) VSE (max) VSE (min.) VOL (min.) VSS Figure 9-7. EOP Transaction Voltage Levels The width of the SE0 in the EOP is about two bit times. The EOP width is measured with the same capacitive load used for maximum rise and fall times and is measured at the same level as the differential signal crossover points of the data lines.
Universal Serial Bus Module (USB) The reset flag bit (RSTF) in the USB interrupt register 1 (UIR1) also will be set after the internal reset is removed. Refer to 9.8.3 USB Interrupt Register 1 for more detail. After a reset is removed, the device will be in the default, but not yet addressed or configured state (refer to Section 9.1 USB Device States of the Universal Serial Bus Specification Rev. 1.1). The device must be able to accept a device address via a SET_ADDRESS command (refer to Section 9.
Universal Serial Bus Module (USB) Functional Description 9.5.4 Resume After Suspend The MCU can be activated from the suspend state by normal bus activity, a USB reset signal, or by a forced resume driven from the MCU. 9.5.4.1 Host Initiated Resume The host signals resume by initiating resume signalling (K state) for at least 20ms followed by a standard low-speed EOP signal. This 20ms ensures that all devices in the USB network are awakened.
Universal Serial Bus Module (USB) 9.5.5 Low-Speed Device Low-speed devices are configured by the position of a pull-up resistor on the USB D– pin of the MCU. Low-speed devices are terminated as shown in Figure 9-9 with the pull-up on the D– line. VREG (3.3V) MCU 1.5 kΩ D+ USB LOW-SPEED CABLE D– Figure 9-9. External Low-Speed Device Configuration For low-speed transmissions, the transmitter’s EOP width must be between 1.25µs and 1.50µs.
Universal Serial Bus Module (USB) Hardware Description 9.7 Hardware Description The USB module as previously shown in Figure 9-2 contains three functional blocks: the low-speed USB transceiver, the USB control logic, and the USB registers. The following details the function of the regulator, transceiver, and control logic. See 9.8 I/O Registers for details of register settings. 9.7.1 Voltage Regulator The USB data lines are required by the USB specification to have an output voltage between 2.8V and 3.6V.
Universal Serial Bus Module (USB) 9.7.2.1 Output Driver Characteristics The USB transceiver uses a differential output driver to drive the USB data signal onto the USB cable. The static output swing of the driver in its low state is below the VOL of 0.3V with a 1.5kΩ load to 3.6V and in its high state is above the VOH of 2.8V with a 15kΩ load to ground. The output swings between the differential high and low state are well balanced to minimize signal skew.
Universal Serial Bus Module (USB) Hardware Description The receiver features an input sensitivity of 200mV when both differential data inputs are in the differential common mode range of 0.8V to 2.5V as shown in Figure 9-12. In addition to the differential receiver, there is a single-ended receiver (schmitt trigger) for each of the two data lines. Differential Input voltage Range Differential Output Crossover Voltage Range –1.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.
Universal Serial Bus Module (USB) tPeriod CROSSOVER POINTS DIFFERENTIAL DATA LINES JITTER CONSECUTIVE TRANSITIONS PAIRED TRANSITIONS Figure 9-13. Data Jitter For low-speed transmissions, the jitter time for any consecutive differential data transitions must be within ±25ns and within ±10ns for any set of paired differential data transitions.
Universal Serial Bus Module (USB) I/O Registers 9.7.3 USB Control Logic The USB control logic manages data movement between the CPU and the transceiver. The control logic handles both transmit and receive operations on the USB. It contains the logic used to manipulate the transceiver and the endpoint registers. The byte count buffer is loaded with the active transmit endpoints byte count value during transmit operations.
Universal Serial Bus Module (USB) 9.8.1 USB Address Register Address: $0038 Bit 7 6 5 4 3 2 1 Bit 0 USBEN UADD6 UADD5 UADD4 UADD3 UADD2 UADD1 UADD0 0* 0 0 0 0 0 0 0 Read: Write: Reset: * USBEN bit is reset by POR or LVI reset only. Figure 9-15. USB Address Register (UADDR) USBEN — USB Module Enable This read/write bit enables and disables the USB module and the USB pins. When USBEN is set, the USB module is enabled and the PTE4 interrupt is disabled.
Universal Serial Bus Module (USB) I/O Registers 9.8.2 USB Interrupt Register 0 Address: $0039 Bit 7 6 5 4 3 EOPIE SUSPND TXD2IE RXD2IE TXD1IE 0 0 0 0 0 Read: 2 1 Bit 0 TXD0IE RXD0IE 0 0 0 Write: Reset: 0 = Unimplemented Figure 9-16. USB Interrupt Register 0 (UIR0) EOPIE — End-of-Packet Detect Interrupt Enable This read/write bit enables the USB to generate CPU interrupt requests when the EOPF bit becomes set. Reset clears the EOPIE bit.
Universal Serial Bus Module (USB) RXD2IE — Endpoint 2 Receive Interrupt Enable This read/write bit enables the receive endpoint 2 to generate CPU interrupt requests when the RXD2F bit becomes set. Reset clears the RXD2IE bit.
Universal Serial Bus Module (USB) I/O Registers 9.8.3 USB Interrupt Register 1 Address: Read: $003A Bit 7 6 5 4 3 2 1 Bit 0 EOPF RSTF TXD2F RXD2F TXD1F RESUMF TXD0F RXD0F 0 0 0 0 0 0 0 0 Write: Reset: = Unimplemented Figure 9-17. USB Interrupt Register 1 (UIR1) EOPF — End-of-Packet Detect Flag This read-only bit is set when a valid end-of-packet sequence is detected on the D+ and D– lines. Software must clear this flag by writing a logic 1 to the EOPFR bit.
Universal Serial Bus Module (USB) To enable the next data packet transmission, TX2E also must be set. If the TXD2F bit is not cleared, a NAK handshake will be returned in the next IN transaction. Reset clears this bit. Writing to TXD2F has no effect. 1 = Transmit on endpoint 2 has occurred 0 = Transmit on endpoint 2 has not occurred RXD2F — Endpoint 2 Data Receive Flag This read-only bit is set after the USB module has received a data packet and responded with an ACK handshake packet.
Universal Serial Bus Module (USB) I/O Registers TXD0F — Endpoint 0 Data Transmit Flag This read-only bit is set after the data stored in endpoint 0 transmit buffers has been sent and an ACK handshake packet from the host is received. Once the next set of data is ready in the transmit buffers, software must clear this flag by writing a logic 1 to the TXD0FR bit. To enable the next data packet transmission, TX0E also must be set.
Universal Serial Bus Module (USB) 9.8.4 USB Interrupt Register 2 Address: $0018 Bit 7 6 5 4 3 2 1 Bit 0 Read: 0 0 0 0 0 0 0 0 Write: EOPFR RSTFR TXD2FR RXD2FR Reset: 0 0 0 0 TXD1FR RESUMFR TXD0FR 0 0 0 RXD0FR 0 Figure 9-18. USB Interrupt Register 2 (UIR2) EOPFR — End-of-Packet Flag Reset Writing a logic 1 to this write-only bit will clear the EOPF bit if it is set. Writing a logic 0 to the EOPFR has no effect. Reset clears this bit.
Universal Serial Bus Module (USB) I/O Registers 9.8.5 USB Control Register 0 Address: $003B Bit 7 Read: 6 5 4 3 2 1 Bit 0 TX0E RX0E TP0SIZ3 TP0SIZ2 TP0SIZ1 TP0SIZ0 0 0 0 0 0 0 0 T0SEQ Write: Reset: 0 0 Figure 9-19. USB Control Register 0 (UCR0) T0SEQ — Endpoint 0 Transmit Sequence Bit This read/write bit determines which type of data packet (DATA0 or DATA1) will be sent during the next IN transaction directed at endpoint 0. Toggling of this bit must be controlled by software.
Universal Serial Bus Module (USB) TP0SIZ3–TP0SIZ0 — Endpoint 0 Transmit Data Packet Size These read/write bits store the number of transmit data bytes for the next IN token request for endpoint 0. These bits are cleared by reset. 9.8.6 USB Control Register 1 Address: $003C Bit 7 6 5 T1SEQ STALL1 TX1E 0 0 0 4 3 2 1 Bit 0 TP1SIZ2 TP1SIZ1 TP1SIZ0 0 0 0 Read: FRESUM TP1SIZ3 Write: Reset: 0 0 Figure 9-20.
Universal Serial Bus Module (USB) I/O Registers If this bit is 0 or the TXD1F is set, the USB will respond with a NAK handshake to any endpoint 1 directed IN tokens. Reset clears this bit. 1 = Data is ready to be sent 0 = Data is not ready. Respond with NAK FRESUM — Force Resume This read/write bit forces a resume state (K or non-idle state) onto the USB data lines to initiate a remote wakeup. Software should control the timing of the forced resume to be between 10 and 15 ms.
Universal Serial Bus Module (USB) STALL2 — Endpoint 2 Force Stall Bit This read/write bit causes endpoint 2 to return a STALL handshake when polled by either an IN or OUT token by the USB host controller. Reset clears this bit. 1 = Send STALL handshake 0 = Default TX2E — Endpoint 2 Transmit Enable This read/write bit enables a transmit to occur when the USB host controller sends an IN token to endpoint 2. The appropriate endpoint enable bit, ENABLE2 bit in the UCR3 register, also should be set.
Universal Serial Bus Module (USB) I/O Registers 9.8.8 USB Control Register 3 Address: Read: $001A Bit 7 6 TX1ST 0 Write: Reset: 5 4 OSTALL0 ISTALL0 0 0 3 2 1 Bit 0 0 PULLEN ENABLE2 ENABLE1 TX1STR 0 0 0 0* 0 0 = Unimplemented * PULLEN bit is reset by POR or LVI reset only. Figure 9-22.
Universal Serial Bus Module (USB) ISTALL0 — Endpoint 0 Force STALL Bit for IN token This read/write bit causes endpoint 0 to return a STALL handshake when polled by an IN token by the USB host controller. Reset clears this bit. 1 = Send STALL handshake 0 = Default PULLEN — Pull-up Enable This read/write bit controls the pull-up option for the USB D– pin if the USB module is enabled.
Universal Serial Bus Module (USB) I/O Registers 9.8.9 USB Control Register 4 USB control register 4 directly controls the USB data pins D+ and D–. If the FUSBO bit, and the USBEN bit of the USB address register (UADDR) are set, the output buffers of the USB modules are enabled and the corresponding levels of the USB data pins D+ and D– are equal to the values set by the FDP and the FDM bits.
Universal Serial Bus Module (USB) 9.8.10 USB Status Register 0 Address: Read: $003D Bit 7 6 5 4 3 2 1 Bit 0 R0SEQ SETUP 0 0 RP0SIZ3 RP0SIZ2 RP0SIZ1 RP0SIZ0 Write: Reset: Unaffected by reset = Unimplemented Figure 9-24. USB Status Register 0 (USR0) R0SEQ — Endpoint 0 Receive Sequence Bit This read-only bit indicates the type of data packet last received for endpoint 0 (DATA0 or DATA1).
Universal Serial Bus Module (USB) I/O Registers 9.8.11 USB Status Register 1 Address: Read: $003E Bit 7 6 5 4 3 2 1 Bit 0 R2SEQ TXACK TXNAK TXSTL RP2SIZ3 RP2SIZ2 RP2SIZ1 RP2SIZ0 U 0 0 0 U U U U Write: Reset: = Unimplemented U = Unaffected by reset Figure 9-25. USB Status Register 1 (USR1) R2SEQ — Endpoint 2 Receive Sequence Bit This read-only bit indicates the type of data packet last received for endpoint 2 (DATA0 or DATA1).
Universal Serial Bus Module (USB) 9.8.12 USB Endpoint 0 Data Registers Address: $0020 UE0D0 Bit 7 6 5 4 3 2 1 Bit 0 Read: UE0R07 UE0R06 UE0R05 UE0R04 UE0R03 UE0R02 UE0R01 UE0R00 Write: UE0T07 UE0T06 UE0T05 UE0T04 UE0T03 UE0T02 UE0T01 UE0T00 Reset: Unaffected by reset ↓ Address: $0027 ↓ UE0D7 Read: UE0R77 UE0R76 UE0R75 UE0R74 UE0R73 UE0R72 UE0R71 UE0R70 Write: UE0T77 UE0T76 UE0T75 UE0T74 UE0T73 UE0T72 UE0T71 UE0T70 Reset: Unaffected by reset Figure 9-26.
Universal Serial Bus Module (USB) I/O Registers 9.8.13 USB Endpoint 1 Data Registers Address: $0028 UE1D0 Bit 7 6 5 4 3 2 1 Bit 0 UE1T06 UE1T05 UE1T04 UE1T03 UE1T02 UE1T01 UE1T00 Read: Write: UE1T07 Reset: Unaffected by reset ↓ Address: $002F ↓ UE1D7 Read: Write: UE1T77 UE1T76 UE1T75 Reset: UE1T74 UE1T73 UE1T72 UE1T71 UE1T70 Unaffected by reset = Unimplemented Figure 9-27.
Universal Serial Bus Module (USB) 9.8.14 USB Endpoint 2 Data Registers Address: $0030 UE2D0 Bit 7 6 5 4 3 2 1 Bit 0 Read: UE2R07 UE2R06 UE2R05 UE2R04 UE2R03 UE2R02 UE2R01 UE2R00 Write: UE2T07 UE2T06 UE2T05 UE2T04 UE2T03 UE2T02 UE2T01 UE2T00 Reset: Unaffected by reset ↓ Address: $0037 ↓ UE2D7 Read: UE2R77 UE2R76 UE2R75 UE2R74 UE2R73 UE2R72 UE2R71 UE2R70 Write: UE2T77 UE2T76 UE2T75 UE2T74 UE2T73 UE2T72 UE2T71 UE2T70 Reset: Unaffected by reset Figure 9-28.
Universal Serial Bus Module (USB) USB Interrupts 9.9 USB Interrupts The USB module is capable of generating interrupts and causing the CPU to execute the USB interrupt service routine. There are three types of USB interrupts: • End-of-transaction interrupts signify either a completed transaction receive or transmit transaction. • Resume interrupts signify that the USB bus is reactivated after having been suspended. • End-of-packet interrupts signify that a low-speed end-of-packet signal was detected.
Universal Serial Bus Module (USB) 9.9.1.1 Receive Control Endpoint 0 For a control OUT transaction directed at endpoint 0, the USB module will generate an interrupt by setting the RXD0F flag in the UIR0 register. The conditions necessary for the interrupt to occur are shown in the flowchart in Figure 9-29.
Universal Serial Bus Module (USB) USB Interrupts SETUP transactions cannot be stalled by the USB function. A SETUP received by a control endpoint will clear the ISTALL0 and OSTALL0 bits. The conditions for receiving a SETUP interrupt are shown in Figure 9-30.
Universal Serial Bus Module (USB) 9.9.1.2 Transmit Control Endpoint 0 For a control IN transaction directed at endpoint 0, the USB module will generate an interrupt by setting the TXD0F flag in the UIR1 register. The conditions necessary for the interrupt to occur are shown in the flowchart in Figure 9-31.
Universal Serial Bus Module (USB) USB Interrupts 9.9.1.3 Transmit Endpoint 1 For an IN transaction directed at endpoint 1, the USB module will generate an interrupt by setting the TXD1F in the UIR1 register. The conditions necessary for the interrupt to occur are shown in Figure 9-32.
Universal Serial Bus Module (USB) 9.9.1.4 Transmit Endpoint 2 For an IN transaction directed at endpoint 2, the USB module will generate an interrupt by setting the TXD2F in the UIR1 register. 9.9.1.5 Receive Endpoint 2 For an OUT transaction directed at endpoint 2, the USB module will generate an interrupt by setting the RXD2F in the UIR1 register. 9.9.2 Resume Interrupt The USB module will generate a CPU interrupt if low-speed bus activity is detected after entering the suspend state.
Technical Data — MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 Section 10. Monitor ROM (MON) 10.1 Contents 10.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 10.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 10.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164 10.4.1 Entering Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 10.4.2 Baud Rate . . . . . .
Monitor ROM (MON) 10.
Monitor ROM (MON) Functional Description VDD 10k Ω VDD + VHI RST 0.1 µF 10k Ω HC908JB8 SW2 C (SEE NOTE 2) IRQ D VREG + 4.7 µF 0.1 µF VDD VDD 6MHz VDD 0.1 µF VSS (SEE NOTE 3) 10 µF 10 µF MC145407 + + E 20 + 3 18 4 17 2 19 SW3 fXCLK 6MHz 10 µF 20 pF OSC1 F E 10MΩ 1 OSC2 F + 10 µF VDD 3.3V 20 pF 10 kΩ DB-25 2 3 A 5 6 16 (SEE NOTE 1) SW1 PTA3 B 15 3.3V 7 1 MC74LCX125 3.3V 14 2 3 6 5 10 kΩ 4 PTA0 3.3V 10 kΩ 7 PTA1 PTA2 NOTES: 1.
Monitor ROM (MON) 10.4.1 Entering Monitor Mode Table 10-1 shows the pin conditions for entering monitor mode. As specified in the table, monitor mode may be entered after a POR and will allow communication at 9600 baud provided one of the following sets of conditions is met: 1. If IRQ = VDD + VHI: – External clock on OSC1 is 3MHz – PTA3 = low 2. If IRQ = VDD + VHI: – External clock on OSC1 is 6MHz – PTA3 = high 3.
Monitor ROM (MON) Functional Description If VDD +VHI is applied to IRQ and PTA3 is low upon monitor mode entry (Table 10-1 condition set 1), the bus frequency is a equal to the external clock, fXCLK. If PTA3 is high with VDD +VHI applied to IRQ upon monitor mode entry (Table 10-1 condition set 2), the bus frequency is a divideby-two of the external clock. Holding the PTA3 pin low when entering monitor mode causes a bypass of a divide-by-two stage at the oscillator only if VDD +VHI is applied to IRQ.
Monitor ROM (MON) POR RESET IS VECTOR BLANK? NO NORMAL USER MODE YES MONITOR MODE EXECUTE MONITOR CODE POR TRIGGERED? NO YES Figure 10-2. Low-Voltage Monitor Mode Entry Flowchart Enter monitor mode with the pin configuration shown above by pulling RST low and then high. The rising edge of RST latches monitor mode. Once monitor mode is latched, the values on the specified pins can change. Once out of reset, the MCU waits for the host to send eight security bytes. (See 10.5 Security.
Monitor ROM (MON) Functional Description Table 10-2 is a summary of the vector differences between user mode and monitor mode. Table 10-2. Monitor Mode Vector Differences Functions COP Reset Vector High Reset Vector Low Break Vector High Break Vector Low SWI Vector High SWI Vector Low User Enabled $FFFE $FFFF $FFFC $FFFD $FFFC $FFFD Monitor Disabled(1) $FEFE $FEFF $FEFC $FEFD $FEFC $FEFD Modes Notes: 1.
Monitor ROM (MON) 10.4.3 Data Format Communication with the monitor ROM is in standard non-return-to-zero (NRZ) mark/space data format. (See Figure 10-3 and Figure 10-4.) START BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 STOP BIT BIT 7 NEXT START BIT Figure 10-3. Monitor Data Format $A5 START BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BREAK START BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 STOP BIT STOP BIT NEXT START BIT NEXT START BIT Figure 10-4.
Monitor ROM (MON) Functional Description 10.4.5 Break Signal A start bit followed by nine low bits is a break signal. (See Figure 10-6.) When the monitor receives a break signal, it drives the PTA0 pin high for the duration of two bits before echoing the break signal. MISSING STOP BIT TWO-STOP-BIT DELAY BEFORE ZERO ECHO 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 Figure 10-6. Break Transaction 10.4.
Monitor ROM (MON) Table 10-4. READ (Read Memory) Command Description Read byte from memory Operand Specifies 2-byte address in high byte:low byte order Data Returned Returns contents of specified address Opcode $4A Command Sequence SENT TO MONITOR READ READ ADDR. HIGH ADDR. HIGH ADDR. LOW ADDR. LOW ECHO DATA RESULT Table 10-5.
Monitor ROM (MON) Functional Description Table 10-6. IREAD (Indexed Read) Command Description Read next 2 bytes in memory from last address accessed Operand Specifies 2-byte address in high byte:low byte order Data Returned Returns contents of next two addresses Opcode $1A Command Sequence SENT TO MONITOR IREAD IREAD DATA DATA RESULT ECHO Table 10-7.
Monitor ROM (MON) Table 10-8. READSP (Read Stack Pointer) Command Description Reads stack pointer Operand None Data Returned Returns stack pointer in high byte:low byte order Opcode $0C Command Sequence SENT TO MONITOR READSP READSP SP HIGH SP LOW RESULT ECHO Table 10-9.
Monitor ROM (MON) Security 10.5 Security A security feature discourages unauthorized reading of FLASH locations while in monitor mode. The host can bypass the security feature at monitor mode entry by sending eight security bytes that match the bytes at locations $FFF6–$FFFD. Locations $FFF6–$FFFD contain userdefined data. NOTE: Do not leave locations $FFF6–$FFFD blank. For security reasons, program locations $FFF6–$FFFD even if they are not used for vectors.
Monitor ROM (MON) Upon power-on reset, if the received bytes of the security code do not match the data at locations $FFF6–$FFFD, the host fails to bypass the security feature. The MCU remains in monitor mode, but reading a FLASH location returns an invalid value and trying to execute code from FLASH causes an illegal address reset. After receiving the eight security bytes from the host, the MCU transmits a break character, signifying that it is ready to receive a command.
Technical Data — MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 Section 11. Timer Interface Module (TIM) 11.1 Contents 11.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 11.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 11.4 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 11.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179 11.5.
Timer Interface Module (TIM) 11.2 Introduction This section describes the timer interface module (TIM2, Version B). The TIM is a 2-channel timer that provides a timing reference with input capture, output compare, and pulse-width-modulation functions. Figure 11-1 is a block diagram of the TIM. 11.
Timer Interface Module (TIM) Functional Description 11.5 Functional Description Figure 11-1 shows the structure of the TIM. The central component of the TIM is the 16-bit TIM counter that can operate as a free-running counter or a modulo up-counter. The TIM counter provides the timing reference for the input capture and output compare functions. The TIM counter modulo registers, TMODH:TMODL, control the modulo value of the TIM counter.
Timer Interface Module (TIM) Addr.
Timer Interface Module (TIM) Functional Description $0014 $0015 TIM Channel 1 Register High (TCH1H) TIM Channel 1 Register Low (TCH1L) Read: Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit2 Bit1 Bit0 Write: Reset: Indeterminate after reset Read: Bit7 Bit6 Bit5 Bit4 Bit3 Write: Reset: Indeterminate after reset = Unimplemented Figure 11-2. TIM I/O Register Summary 11.5.
Timer Interface Module (TIM) 11.5.3.1 Unbuffered Output Compare Any output compare channel can generate unbuffered output compare pulses as described in 11.5.3 Output Compare. The pulses are unbuffered because changing the output compare value requires writing the new value over the old value currently in the TIM channel registers. An unsynchronized write to the TIM channel registers to change an output compare value could cause incorrect operation for up to two counter overflow periods.
Timer Interface Module (TIM) Functional Description 11.5.3.2 Buffered Output Compare Channels 0 and 1 can be linked to form a buffered output compare channel whose output appears on the PTE1/TCH0 pin. The TIM channel registers of the linked pair alternately control the output. Setting the MS0B bit in TIM channel 0 status and control register (TSC0) links channel 0 and channel 1. The output compare value in the TIM channel 0 registers initially controls the output on the PTE1/TCH0 pin.
Timer Interface Module (TIM) OVERFLOW OVERFLOW OVERFLOW PERIOD PULSE WIDTH PTEx/TCHxA OUTPUT COMPARE OUTPUT COMPARE OUTPUT COMPARE Figure 11-3. PWM Period and Pulse Width The value in the TIM counter modulo registers and the selected prescaler output determines the frequency of the PWM output. The frequency of an 8-bit PWM signal is variable in 256 increments.
Timer Interface Module (TIM) Functional Description Use the following methods to synchronize unbuffered changes in the PWM pulse width on channel x: NOTE: • When changing to a shorter pulse width, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. The output compare interrupt occurs at the end of the current pulse. The interrupt routine has until the end of the PWM period to write the new value.
Timer Interface Module (TIM) NOTE: In buffered PWM signal generation, do not write new pulse width values to the currently active channel registers. User software should track the currently active channel to prevent writing a new value to the active channel. Writing to the active channel registers is the same as generating unbuffered PWM signals. 11.5.4.3 PWM Initialization To ensure correct operation when generating unbuffered or buffered PWM signals, use this initialization procedure: 1.
Timer Interface Module (TIM) Interrupts Setting MS0B links channels 0 and 1 and configures them for buffered PWM operation. The TIM channel 0 registers (TCH0H:TCH0L) initially control the buffered PWM output. TIM status control register 0 (TSCR0) controls and monitors the PWM signal from the linked channels. MS0B takes priority over MS0A. Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on TIM overflows.
Timer Interface Module (TIM) 11.7.1 Wait Mode The TIM remains active after the execution of a WAIT instruction. In wait mode the TIM registers are not accessible by the CPU. Any enabled CPU interrupt request from the TIM can bring the MCU out of wait mode. If TIM functions are not required during wait mode, reduce power consumption by stopping the TIM before executing the WAIT instruction. 11.7.2 Stop Mode The TIM is inactive after the execution of a STOP instruction.
Timer Interface Module (TIM) I/O Signals 11.9 I/O Signals Port E shares three of its pins with the TIM. PTE0/TCLK is an external clock input to the TIM prescaler. The two TIM channel I/O pins are PTE1/TCH0 and PTE2/TCH1. 11.9.1 TIM Clock Pin (PTE0/TCLK) PTE0/TCLK is an external clock input that can be the clock source for the TIM counter instead of the prescaled internal bus clock. Select the PTE0/TCLK input by writing logic 1s to the three prescaler select bits, PS[2:0]. (See 11.10.
Timer Interface Module (TIM) 11.10.1 TIM Status and Control Register The TIM status and control register: • Enables TIM overflow interrupts • Flags TIM overflows • Stops the TIM counter • Resets the TIM counter • Prescales the TIM counter clock Address: $000A Bit 7 Read: 6 5 TOIE TSTOP TOF Write: 0 Reset: 0 4 3 0 0 2 1 Bit 0 PS2 PS1 PS0 0 0 0 TRST 0 1 0 0 = Unimplemented Figure 11-4.
Timer Interface Module (TIM) I/O Registers TSTOP — TIM Stop Bit This read/write bit stops the TIM counter. Counting resumes when TSTOP is cleared. Reset sets the TSTOP bit, stopping the TIM counter until software clears the TSTOP bit. 1 = TIM counter stopped 0 = TIM counter active NOTE: Do not set the TSTOP bit before entering wait mode if the TIM is required to exit wait mode. TRST — TIM Reset Bit Setting this write-only bit resets the TIM counter and the TIM prescaler.
Timer Interface Module (TIM) 11.10.2 TIM Counter Registers The two read-only TIM counter registers contain the high and low bytes of the value in the TIM counter. Reading the high byte (TCNTH) latches the contents of the low byte (TCNTL) into a buffer. Subsequent reads of TCNTH do not affect the latched TCNTL value until TCNTL is read. Reset clears the TIM counter registers. Setting the TIM reset bit (TRST) also clears the TIM counter registers.
Timer Interface Module (TIM) I/O Registers 11.10.3 TIM Counter Modulo Registers The read/write TIM modulo registers contain the modulo value for the TIM counter. When the TIM counter reaches the modulo value, the overflow flag (TOF) becomes set, and the TIM counter resumes counting from $0000 at the next timer clock. Writing to the high byte (TMODH) inhibits the TOF bit and overflow interrupts until the low byte (TMODL) is written. Reset sets the TIM counter modulo registers.
Timer Interface Module (TIM) 11.10.
Timer Interface Module (TIM) I/O Registers CHxF — Channel x Flag Bit When channel x is an input capture channel, this read/write bit is set when an active edge occurs on the channel x pin. When channel x is an output compare channel, CHxF is set when the value in the TIM counter registers matches the value in the TIM channel x registers.
Timer Interface Module (TIM) When ELSxB:ELSxA = 0:0, this read/write bit selects the initial output level of the TCHx pin. (See Table 11-3.) Reset clears the MSxA bit. 1 = Initial output level low 0 = Initial output level high NOTE: Before changing a channel function by writing to the MSxB or MSxA bit, set the TSTOP and TRST bits in the TIM status and control register (TSC).
Timer Interface Module (TIM) I/O Registers NOTE: Before enabling a TIM channel register for input capture operation, make sure that the PTEx/TCHx pin is stable for at least two bus clocks. TOVx — Toggle-On-Overflow Bit When channel x is an output compare channel, this read/write bit controls the behavior of the channel x output when the TIM counter overflows. When channel x is an input capture channel, TOVx has no effect. Reset clears the TOVx bit.
Timer Interface Module (TIM) 11.10.5 TIM Channel Registers These read/write registers contain the captured TIM counter value of the input capture function or the output compare value of the output compare function. The state of the TIM channel registers after reset is unknown. In input capture mode (MSxB:MSxA = 0:0), reading the high byte of the TIM channel x registers (TCHxH) inhibits input captures until the low byte (TCHxL) is read.
Technical Data — MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 Section 12. Input/Output Ports (I/O) 12.1 Contents 12.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 12.3 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 12.3.1 Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 12.3.2 Data Direction Register A. . . . . . . . . . . . . . . . . . . . . . . . . . 203 12.4 Port B . . . . . .
Input/Output Ports (I/O) NOTE: Connect any unused I/O pins to an appropriate logic level, either VREG or VSS. Although the I/O ports do not require termination for proper operation, termination reduces excess current consumption and the possibility of electrostatic damage. Addr.
Input/Output Ports (I/O) Introduction Addr. Register Name Bit 7 6 5 $0009 Data Direction Register E Read: (DDRE) Write: 0 0 0 Reset: 0 0 0 $001D Read: Port Option Control PTE20P Register Write: (POCR) Reset: 0 PTDLDD PTDILDD 0 4 3 2 1 Bit 0 DDRE4 DDRE3 DDRE2 DDRE1 DDRE0 0 0 0 0 0 PTE4P PTE3P PCP PBP PAP 0 0 0 0 0 0 = Unimplemented Figure 12-1. I/O Port Register Summary Table 12-1.
Input/Output Ports (I/O) 12.3 Port A Port A is an 8-bit general-purpose bidirectional I/O port with software configurable pullups, and it shares its pins with the keyboard interrupt module (KBI). 12.3.1 Port A Data Register The port A data register contains a data latch for each of the eight port A pins.
Input/Output Ports (I/O) Port A 12.3.2 Data Direction Register A Data direction register A determines whether each port A pin is an input or an output. Writing a logic 1 to a DDRA bit enables the output buffer for the corresponding port A pin; a logic 0 disables the output buffer. Address: $0004 Bit 7 6 5 4 3 2 1 Bit 0 DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0 0* 0 0 0 0 0 0 0 Read: Write: Reset: * DDRA7 bit is reset by POR or LVI reset only. Figure 12-3.
Input/Output Ports (I/O) When bit DDRAx is a logic 1, reading address $0000 reads the PTAx data latch. When bit DDRAx is a logic 0, reading address $0000 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 12-2 summarizes the operation of the port A pins. Table 12-2.
Input/Output Ports (I/O) Port B PTB[7:0] — Port B Data Bits These read/write bits are software-programmable. Data direction of each port B pin is under the control of the corresponding bit in data direction register B. Reset has no effect on port B data. The port B pullup enable bit, PBP, in the port option control register (POCR) enables pullups on port B pins if the respective pin is configured as an input. (See 12.8 Port Options.) 12.4.
Input/Output Ports (I/O) READ DDRB ($0005) INTERNAL DATA BUS WRITE DDRB ($0005) DDRBx RESET WRITE PTB ($0001) PTBx PTBx READ PTB ($0001) Figure 12-7. Port B I/O Circuit When bit DDRBx is a logic 1, reading address $0001 reads the PTBx data latch. When bit DDRBx is a logic 0, reading address $0001 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 12-3 summarizes the operation of the port B pins. Table 12-3.
Input/Output Ports (I/O) Port C 12.5 Port C Port C is an 8-bit general-purpose bidirectional I/O port with software configurable pullups and current drive options. 12.5.1 Port C Data Register The port C data register contains a data latch for each of the eight port C pins. NOTE: PTC7–PTC1 are not available in the 20-pin PDIP, 20-pin SOIC, and 28-pin SOIC packages.
Input/Output Ports (I/O) 12.5.2 Data Direction Register C Data direction register C determines whether each port C pin is an input or an output. Writing a logic 1 to a DDRC bit enables the output buffer for the corresponding port C pin; a logic 0 disables the output buffer. Address: $0006 Bit 7 6 5 4 3 2 1 Bit 0 DDRC7 DDRC6 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0 0 0 0 0 0 0 0 0 Read: Write: Reset: Figure 12-9.
Input/Output Ports (I/O) Port D READ DDRC ($0006) INTERNAL DATA BUS WRITE DDRC ($0006) DDRCx RESET WRITE PTC ($0002) PTCx PTCx READ PTC ($0002) Figure 12-10. Port C I/O Circuit When bit DDRCx is a logic 1, reading address $0002 reads the PTCx data latch. When bit DDRCx is a logic 0, reading address $0002 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 12-4 summarizes the operation of the port C pins. Table 12-4.
Input/Output Ports (I/O) 12.6.1 Port D Data Register The port D data register contains a data latch for each of the eight port D pins. NOTE: PTD7–PTD2 are not available in the 20-pin PDIP and 20-pin SOIC packages. PTD7 is not available in the 28-pin SOIC package.
Input/Output Ports (I/O) Port D 12.6.2 Data Direction Register D Data direction register D determines whether each port D pin is an input or an output. Writing a logic 1 to a DDRD bit enables the output buffer for the corresponding port D pin; a logic 0 disables the output buffer. Address: $0007 Bit 7 6 5 4 3 2 1 Bit 0 DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0 0 0 0 0 0 0 0 0 Read: Write: Reset: Figure 12-12.
Input/Output Ports (I/O) READ DDRD ($0007) INTERNAL DATA BUS WRITE DDRD ($0007) DDRDx RESET WRITE PTD ($0003) PTDx PTDx READ PTD ($0003) Figure 12-13. Port D I/O Circuit When bit DDRDx is a logic 1, reading address $0003 reads the PTDx data latch. When bit DDRDx is a logic 0, reading address $0003 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 12-5 summarizes the operation of the port D pins. Table 12-5.
Input/Output Ports (I/O) Port E 12.7.1 Port E Data Register The port E data register contains a data latch for each of the five port E pins. NOTE: PTE2 and PTE0 are not available in the 20-pin PDIP and 20-pin SOIC packages.
Input/Output Ports (I/O) PTE4 pin functions as an external interrupt when PTE4IE=1 in the IRQ option control register (IOCR) and USBEN=0 in the USB address register (USB disabled). (See 13.9 IRQ Option Control Register.) D– and D+ — USB Data Pins D– and D+ are the differential data lines used by the USB module. (See Section 9. Universal Serial Bus Module (USB).) The USB module enable bit, USBEN, in the USB address register (UADDR) controls the pin options for PTE4/D– and PTE3/D+.
Input/Output Ports (I/O) Port E 12.7.2 Data Direction Register E Data direction register E determines whether each port E pin is an input or an output. Writing a logic 1 to a DDRE bit enables the output buffer for the corresponding port E pin; a logic 0 disables the output buffer. Address: Read: $0009 Bit 7 6 5 0 0 0 4 3 2 1 Bit 0 DDRE4 DDRE3 DDRE2 DDRE1 DDRE0 0 0 0 0 0 Write: Reset: 0 0 0 = Unimplemented Figure 12-15.
Input/Output Ports (I/O) READ DDRE ($000C) INTERNAL DATA BUS WRITE DDRE ($000C) DDREx RESET WRITE PTE ($0008) PTEx PTEx READ PTE ($0008) Figure 12-16. Port E I/O Circuit When bit DDREx is a logic 1, reading address $0008 reads the PTEx data latch. When bit DDREx is a logic 0, reading address $0008 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 12-4 summarizes the operation of the port E pins. Table 12-6.
Input/Output Ports (I/O) Port Options 12.8.1 Port Option Control Register The port option control register controls the pullup options for port A, B, C, and E pins. It also controls the drive configuration on port D. Address: $001D Bit 7 6 5 4 3 2 1 Bit 0 PTE4P PTE3P PCP PBP PAP 0 0 0 0 0 Read: PTE20P PTDLDD PTDILDD Write: Reset: 0 0 0 Figure 12-17.
Input/Output Ports (I/O) PTE4P — Pin PTE4 Pullup Enable This read/write bit controls the pullup option for the PTE4 pin when the pin is configured as an input and the USB module is disabled. 1 = Configure PTE4 to have internal pullup to VDD 0 = Disconnect PTE4 internal pullup NOTE: When the USB module is enabled, the pullup controlled by PTE4P is disconnected; PTE4/D– pin functions as D– which has a 1.5kΩ programmable pullup resistor. (See 9.8.8 USB Control Register 3.
Technical Data — MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 Section 13. External Interrupt (IRQ) 13.1 Contents 13.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 13.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 13.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220 13.5 IRQ Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 13.
External Interrupt (IRQ) 13.4 Functional Description A logic 0 applied to the external interrupt pin can latch a CPU interrupt request. Figure 13-1 shows the structure of the IRQ module. Interrupt signals on the IRQ pin are latched into the IRQ latch. An interrupt latch remains set until one of the following actions occurs: • Vector fetch — A vector fetch automatically generates an interrupt acknowledge signal that clears the IRQ latch.
External Interrupt (IRQ) Functional Description INTERNAL ADDRESS BUS ACK RESET VECTOR FETCH DECODER HIGH VOLTAGE DETECT TO MODE SELECT LOGIC TO CPU FOR BIL/BIH INSTRUCTIONS VDD IRQPD "1" IRQF INTERNAL PULLUP D DEVICE IRQ CLR Q SYNCHRONIZER CK IRQ INTERRUPT REQUEST IRQ FF IMASK MODE TO PTE4 PULLUP ENABLE CIRCUITRY "1" READ IOCR D PTE4 CLR Q PTE4IF CK PTE4IE Figure 13-1. IRQ Module Block Diagram Addr.
External Interrupt (IRQ) 13.5 IRQ Pin The IRQ pin has a low leakage for input voltages ranging from 0V to VDD; suitable for applications using RC discharge circuitry to wake up the MCU. A logic 0 on the IRQ pin can latch an interrupt request into the IRQ latch. A vector fetch, software clear, or reset clears the IRQ latch. If the MODE bit is set, the IRQ pin is both falling-edge-sensitive and lowlevel-sensitive.
External Interrupt (IRQ) PTE4/D– Pin Use the BIH or BIL instruction to read the logic level on the IRQ pin. NOTE: When using the level-sensitive interrupt trigger, avoid false interrupts by masking interrupt requests in the interrupt routine. NOTE: An internal pullup resistor to VDD is connected to IRQ pin; this can be disabled by setting the IRQPD bit in the IRQ option control register ($001C). 13.
External Interrupt (IRQ) 13.8 IRQ Status and Control Register The IRQ status and control register (ISCR) controls and monitors operation of the IRQ module. The ISCR has the following functions: • Shows the state of the IRQ flag • Clears the IRQ latch • Masks IRQ interrupt request • Controls triggering sensitivity of the IRQ pin Address: Read: $001E Bit 7 6 5 4 3 2 0 0 0 0 IRQF 0 Write: Reset: 1 Bit 0 IMASK MODE 0 0 ACK 0 0 0 0 0 0 = Unimplemented Figure 13-3.
External Interrupt (IRQ) IRQ Option Control Register 0 = IRQ interrupt requests on falling edges only 13.9 IRQ Option Control Register The IRQ option control register controls and monitors the external interrupt function available on the PTE4 pin. It also disables/enables the pullup resistor on the IRQ pin.
External Interrupt (IRQ) This read/write bit controls the pullup option for the IRQ pin. 1 = Internal pullup is disconnected 0 = Internal pull-up is connected between IRQ pin and VDD Technical Data 226 MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.
Technical Data — MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 Section 14. Keyboard Interrupt Module (KBI) 14.1 Contents 14.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 14.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 14.4 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 14.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .230 14.
Keyboard Interrupt Module (KBI) 14.3 Features Features of the keyboard interrupt module include: • Eight keyboard interrupt pins with separate keyboard interrupt enable bits and one keyboard interrupt mask • Hysteresis buffers • Programmable edge-only or edge- and level-interrupt sensitivity • Exit from low-power modes 14.4 Pin Name Conventions The KBI share eight I/O pins with eight port A I/O pins. The full name of the I/O pins are listed in Table 14-1.
Keyboard Interrupt Module (KBI) Pin Name Conventions INTERNAL BUS KBA0 ACKK VREG VECTOR FETCH DECODER KEYF RESET . KBIE0 D CLR Q SYNCHRONIZER . Keyboard Interrupt Request CK TO PULLUP ENABLE . KEYBOARD INTERRUPT FF KBA7 IMASKK MODEK KBIE7 TO PULLUP ENABLE Figure 14-1. Keyboard Module Block Diagram Table 14-2. I/O Register Summary Addr.
Keyboard Interrupt Module (KBI) 14.5 Functional Description Writing to the KBIE7–KBIE0 bits in the keyboard interrupt enable register independently enables or disables each port A pin as a keyboard interrupt pin. Enabling a keyboard interrupt pin also enables its internal pullup device. A logic 0 applied to an enabled keyboard interrupt pin latches a keyboard interrupt request. A keyboard interrupt is latched when one or more keyboard pins goes low after all were high.
Keyboard Interrupt Module (KBI) Keyboard Initialization • Return of all enabled keyboard interrupt pins to logic 1 — As long as any enabled keyboard interrupt pin is at logic 0, the keyboard interrupt remains set. The vector fetch or software clear and the return of all enabled keyboard interrupt pins to logic 1 may occur in any order. If the MODEK bit is clear, the keyboard interrupt pin is falling-edgesensitive only.
Keyboard Interrupt Module (KBI) 3. Write to the ACKK bit in the keyboard status and control register to clear any false interrupts. 4. Clear the IMASKK bit. An interrupt signal on an edge-triggered pin can be acknowledged immediately after enabling the pin. An interrupt signal on an edge- and level-triggered interrupt pin must be acknowledged after a delay that depends on the external load. Another way to avoid a false interrupt: 1.
Keyboard Interrupt Module (KBI) Keyboard Module During Break Interrupts 14.8 Keyboard Module During Break Interrupts The system integration module (SIM) controls whether the keyboard interrupt latch can be cleared during the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status bits during the break state. To allow software to clear the keyboard interrupt latch during a break interrupt, write a logic 1 to the BCFE bit.
Keyboard Interrupt Module (KBI) Address: $0016 Read: Bit 7 6 5 4 3 2 0 0 0 0 KEYF 0 Write: Reset: 1 Bit 0 IMASKK MODEK 0 0 ACKK 0 0 0 0 0 0 = Unimplemented Figure 14-2. Keyboard Status and Control Register (KBSCR) Bits 7–4 — Not used These read-only bits always read as logic 0s. KEYF — Keyboard Flag Bit This read-only bit is set when a keyboard interrupt is pending. Reset clears the KEYF bit.
Keyboard Interrupt Module (KBI) I/O Registers 14.9.2 Keyboard Interrupt Enable Register The keyboard interrupt enable register enables or disables each port A pin to operate as a keyboard interrupt pin. Address: $0017 Bit 7 6 5 4 3 2 1 Bit 0 KBIE7 KBIE6 KBIE5 KBIE4 KBIE3 KBIE2 KBIE1 KBIE0 0 0 0 0 0 0 0 0 Read: Write: Reset: Figure 14-3.
Keyboard Interrupt Module (KBI) Technical Data 236 MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.
Technical Data — MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 Section 15. Computer Operating Properly (COP) 15.1 Contents 15.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 15.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238 15.4 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 15.4.1 OSCXCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .239 15.4.
Computer Operating Properly (COP) 15.3 Functional Description Figure 15-1 shows the structure of the COP module. SIM OSCXCLK SIM RESET CIRCUIT RESET VECTOR FETCH RESET STATUS REGISTER COP TIMEOUT CLEAR ALL STAGES INTERNAL RESET SOURCES(1) CLEAR STAGES 5–12 12-BIT SIM COUNTER COPCTL WRITE COP CLOCK COP MODULE 6-BIT COP COUNTER COPEN (FROM SIM) COPD (FROM CONFIG) RESET COPCTL WRITE CLEAR COP COUNTER COP RATE SEL (COPRS FROM CONFIG) NOTE: 1. See SIM section for more details. Figure 15-1.
Computer Operating Properly (COP) I/O Signals NOTE: Service the COP immediately after reset and before entering or after exiting stop mode to guarantee the maximum time before the first COP counter overflow. A COP reset pulls the RST pin low for 32 OSCXCLK cycles and sets the COP bit in the reset status register (RSR). In monitor mode, the COP is disabled if the RST pin or the IRQ is held at VDD + VHI. During the break state, VDD + VHI on the RST pin disables the COP.
Computer Operating Properly (COP) 15.4.4 Power-On Reset The power-on reset (POR) circuit in the SIM clears the COP prescaler 4096 OSCXCLK cycles after power-up. 15.4.5 Internal Reset An internal reset clears the SIM counter and the COP counter. 15.4.6 Reset Vector Fetch A reset vector fetch occurs when the vector address appears on the data bus. A reset vector fetch clears the COP prescaler. 15.4.
Computer Operating Properly (COP) COP Control Register COPRS — COP Rate Select Bit COPRS selects the COP timeout period. Reset clears COPRS. 1 = COP timeout period is (213 – 24) × OSCXOUT cycles 0 = COP timeout period is (218 – 24) × OSCXOUT cycles COPD — COP Disable Bit COPD disables the COP module. 1 = COP module disabled 0 = COP module enabled 15.5 COP Control Register The COP control register is located at address $FFFF and overlaps the reset vector.
Computer Operating Properly (COP) 15.8 Low-Power Modes The WAIT and STOP instructions put the MCU in low-power consumption standby modes. 15.8.1 Wait Mode The COP remains active during wait mode. To prevent a COP reset during wait mode, periodically clear the COP counter in a CPU interrupt routine. 15.8.2 Stop Mode Stop mode turns off the OSCXCLK input to the COP and clears the COP prescaler.
Technical Data — MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 Section 16. Low Voltage Inhibit (LVI) 16.1 Contents 16.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 16.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .243 16.4 LVI Control Register (CONFIG) . . . . . . . . . . . . . . . . . . . . . . .244 16.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 16.5.1 Wait Mode . . . . . . . .
Low Voltage Inhibit (LVI) VDD LVID LOW VDD VDD > VLVR = 0 DETECTOR VDD < VLVR = 1 LVI RESET Figure 16-1. LVI Module Block Diagram 16.4 LVI Control Register (CONFIG) Address: Read: $001F Bit 7 6 0 0 5 4 3 2 1 Bit 0 URSTD LVID SSREC COPRS STOP COPD 0 0 0 0 0 0 Write: Reset: 0 0 One-time writable register after each reset. URSTD and LVID bits are reset by POR or LVI reset only. = Unimplemented Figure 16-2.
Technical Data — MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 Section 17. Break Module (BREAK) 17.1 Contents 17.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 17.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 17.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .246 17.4.1 Flag Protection During Break Interrupts . . . . . . . . . . . . . . . 248 17.4.
Break Module (BREAK) 17.3 Features Features of the break module include the following: • Accessible i/o registers during the break interrupt • CPU-generated break interrupts • Software-generated break interrupts • COP disabling during break interrupts 17.4 Functional Description When the internal address bus matches the value written in the break address registers, the break module issues a breakpoint signal (BKPT) to the SIM.
Break Module (BREAK) Functional Description IAB[15:8] BREAK ADDRESS REGISTER HIGH 8-BIT COMPARATOR IAB[15:0] BKPT (TO SIM) CONTROL 8-BIT COMPARATOR BREAK ADDRESS REGISTER LOW IAB[7:0] Figure 17-1. Break Module Block Diagram Addr.
Break Module (BREAK) 17.4.1 Flag Protection During Break Interrupts The BCFE bit in the break flag control register (BFCR) enables software to clear status bits during the break state. 17.4.2 CPU During Break Interrupts The CPU starts a break interrupt by: • Loading the instruction register with the SWI instruction • Loading the program counter with $FFFC and $FFFD ($FEFC and $FEFD in monitor mode) The break interrupt begins after completion of the CPU instruction in progress.
Break Module (BREAK) Break Module Registers 17.5.2 Stop Mode A break interrupt causes exit from stop mode and sets the SBSW bit in the break status register. See 8.8 SIM Registers. 17.6 Break Module Registers These registers control and monitor operation of the break module: • Break status and control register (BRKSCR) • Break address register high (BRKH) • Break address register low (BRKL) • Break status register (BSR) • Break flag control register (BFCR) 17.6.
Break Module (BREAK) BRKA — Break Active Bit This read/write status and control bit is set when a break address match occurs. Writing a logic 1 to BRKA generates a break interrupt. Clear BRKA by writing a logic 0 to it before exiting the break routine. Reset clears the BRKA bit. 1 = Break address match 0 = No break address match 17.6.2 Break Address Registers The break address registers contain the high and low bytes of the desired breakpoint address. Reset clears the break address registers.
Break Module (BREAK) Break Module Registers Address: $FE00 Bit 7 6 5 4 3 2 R R R R R R Read: 1 Bit 0 SBSW Write: Note(1) Reset: 0 R = Reserved R 1. Writing a logic zero clears SBSW. Figure 17-6. Break Status Register (BSR) SBSW — SIM Break Stop/Wait This read/write bit is set when a break interrupt causes an exit from wait or stop mode. Clear SBSW by writing a logic 0 to it. Reset clears SBSW.
Break Module (BREAK) 17.6.4 Break Flag Control Register (BFCR) The break control register contains a bit that enables software to clear status bits while the MCU is in a break state. Address: $FE03 Bit 7 6 5 4 3 2 1 Bit 0 BCFE R R R R R R R Read: Write: Reset: 0 R = Reserved Figure 17-7. Break Flag Control Register High (BFCR) BCFE — Break Clear Flag Enable Bit This read/write bit enables software to clear status bits by accessing status registers while the MCU is in a break state.
Technical Data — MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 Section 18. Electrical Specifications 18.1 Contents 18.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 18.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . 254 18.4 Functional Operating Range. . . . . . . . . . . . . . . . . . . . . . . . . . 255 18.5 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 18.
Electrical Specifications 18.3 Absolute Maximum Ratings Maximum ratings are the extreme limits to which the MCU can be exposed without permanently damaging it. NOTE: This device is not guaranteed to operate properly at the maximum ratings. Refer to 18.6 DC Electrical Characteristics for guaranteed operating conditions. Characteristic(1) Symbol Value Unit Supply voltage VDD –0.3 to +6.0 V Input voltage PTE4/D–, PTE3/D+ RST, IRQ Others VIN VSS – 1.0 to VDD + 0.3 VSS – 0.3 to VDD + 0.3 VSS – 0.
Electrical Specifications Functional Operating Range 18.4 Functional Operating Range Characteristic Operating temperature range Operating voltage range Symbol Value Unit TA 0 to 70 °C VDD 4.0 to 5.5 V 18.
Electrical Specifications 18.6 DC Electrical Characteristics Characteristic(1) Symbol Min Typ(2) Max Unit Regulator output voltage VREG 3.0 3.3 3.6 V Output high voltage (ILoad = –2.0 mA) PTA0–PTA7, PTB0–PTB7, PTC0–PTC7, PTE0–PTE2 VOH VREG –0.8 — — V Output low voltage (ILoad = 1.6 mA) All I/O pins (ILoad = 25 mA) PTD0–PTD1 in ILDD mode (ILoad = 10 mA) PTE3–PTE4 with USB disabled VOL — — — — — — 0.4 0.5 0.4 Input high voltage All ports, OSC1 IRQ, RST VIH 0.7 × VREG 0.
Electrical Specifications Control Timing NOTES: 1. VDD = 4.0 to 5.5 Vdc, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted. 2. Typical values reflect average measurements at midpoint of voltage range, 25 °C only. 3. Run (operating) IDD measured using external square wave clock source (fXCLK = 6 MHz). All inputs 0.2 V from rail. No dc loads. Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects run IDD. Measured with all modules enabled. 4.
Electrical Specifications 18.9 USB DC Electrical Characteristics Characteristic(1) Symbol Conditions Min Hi-Z state data line leakage ILO 0 V
Electrical Specifications USB Low-Speed Source Electrical Characteristics 18.10 USB Low-Speed Source Electrical Characteristics Characteristic(1) Symbol Conditions Min Typ Max Unit Internal operating frequency fOP — — 3 — MHz Transition time(2) Rise time tR CL = 200 pF 75 — 300 ns CL = 600pF Fall time tF CL = 200 pF 75 — 300 CL = 600pF tRFM tR/tF 80 — 120 % tDRATE 1.5 Mbs ± 1.5% 1.4775 676.8 1.500 666.0 1.5225 656.
Electrical Specifications 18.
Electrical Specifications Memory Characteristics 18.13 Memory Characteristics Characteristic RAM data retention voltage Symbol Min Max Unit VRDR 1.3 — V FLASH block size — 512 Bytes FLASH programming size — 64 Bytes FLASH read bus clock frequency fRead(1) 32 k 8.
Electrical Specifications Technical Data 262 MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.
Technical Data — MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 Section 19. Mechanical Specifications 19.1 Contents 19.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 19.3 44-Pin Plastic Quad Flat Pack (QFP) . . . . . . . . . . . . . . . . . . . 264 19.4 28-Pin Small Outline Integrated Circuit (SOIC) . . . . . . . . . . . 265 19.5 20-Pin Dual In-Line Package (PDIP) . . . . . . . . . . . . . . . . . . . 265 19.6 20-Pin Small Outline Integrated Circuit (SOIC) .
Mechanical Specifications 19.3 44-Pin Plastic Quad Flat Pack (QFP) B L B 33 23 22 S D S V F BASE METAL 0.20 (0.008) DETAIL A DETAIL A M C A–B S S H A–B 0.20 (0.008) B L –B– M –A– D –A–, –B–, –D– 0.05 (0.002) A–B 34 J N D 44 0.20 (0.008) 12 1 11 M C A–B S D S SECTION B–B VIEW ROTATED 90° –D– A 0.20 (0.008) M H A–B S D S S D S 0.05 (0.002) A–B S 0.20 (0.008) M C A–B M DETAIL C C E –H– –C– DATUM PLANE 0.10 (0.004) H SEATING PLANE G NOTES: 1.
Mechanical Specifications 28-Pin Small Outline Integrated Circuit (SOIC) 19.4 28-Pin Small Outline Integrated Circuit (SOIC) NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION.
Mechanical Specifications 19.6 20-Pin Small Outline Integrated Circuit (SOIC) NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.150 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. –A– 20 11 –B– 10X P 0.010 (0.25) 1 M B M 10 20X D 0.
Technical Data — MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 Section 20. Ordering Information 20.1 Contents 20.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 20.3 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 20.2 Introduction This section contains ordering numbers for the MC68HC908JB8. 20.3 MC Order Numbers Table 20-1.
Ordering Information Technical Data 268 MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.
Technical Data — MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 Appendix A. MC68HC08JB8 A.1 Contents A.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 A.3 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 A.4 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 A.5 Reserved Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 A.6 Monitor ROM . . . . . . . . . . .
MC68HC08JB8 A.2 Introduction This section introduces the MC68HC08JB8, the ROM part equivalent to the MC68HC908JB8. The entire data book apply to this ROM device, with exceptions outlined in this appendix. Table A-1. Summary of MC68HC08JB8 and MC68HC908JB8 Differences MC68HC08JB8 MC68HC908JB8 Memory ($DC00–$FBFF) 8,192 bytes ROM 8,192 bytes FLASH User vectors ($FFF0–$FFFF) 16 bytes ROM 16 bytes FLASH Registers at $FE08 and $FF09 Not used; locations are reserved. FLASH related registers.
PTA PTB PTC PTC7–PTC0 (3) PTD PTD7–PTD6 (4) PTD5–PTD2 (4) (5) DDRA DDRB PTB7–PTB0 (3) DDRC CPU REGISTERS PTA7/KBA7 (3) : PTA0/KBA0 (3) ARITHMETIC/LOGIC UNIT (ALU) KEYBOARD INTERRUPT MODULE CONTROL AND STATUS REGISTERS — 64 BYTES TIMER INTERFACE MODULE USER ROM — 8,192 BYTES USER RAM — 256 BYTES BREAK MODULE MONITOR ROM — 464 BYTES LOW VOLTAGE INHIBIT MODULE OSC1 OSC2 DDRD USER ROM VECTORS — 16 BYTES PTD1–PTD0 (4) (6) POWER-ON RESET MODULE OSCILLATOR PTE4/D– (3) (4) (5) (1), (3) IRQ SYS
MC68HC08JB8 $0000 ↓ $003F I/O Registers 64 Bytes $0040 ↓ $013F RAM 256 Bytes $0140 ↓ $DBFF Unimplemented 56,000 Bytes $DC00 ↓ $FBFF ROM 8,192 Bytes $FC00 ↓ $FDFF Unimplemented 512 Bytes $FE00 Break Status Register (BSR) $FE01 Reset Status Register (RSR) $FE02 Reserved $FE03 Break Flag Control Register (BFCR) $FE04 Interrupt Status Register 1 (INT1) $FE05 Reserved $FE06 Reserved $FE07 Reserved $FE08 Reserved $FE09 Reserved $FE0A Reserved $FE0B Reserved $FE0C Break Address
MC68HC08JB8 A.5 Reserved Registers The two registers at $FE08 and $FE09 are reserved locations on the MC68HC08JB8. On the MC68HC908JB8, these two locations are the FLASH control register and the FLASH block protect register respectively. A.6 Monitor ROM The monitor program (monitor ROM: $FE10–$FFDF) on the MC68HC08JB8 is for device testing only. $FC00–$FDFF are unused. A.
MC68HC08JB8 A.7.1 DC Electrical Characteristics Characteristic(1) Symbol Min Typ(2) Max Unit Regulator output voltage VREG 3.0 3.3 3.6 V Output high voltage (ILoad = –2.0 mA) PTA0–PTA7, PTB0–PTB7, PTC0–PTC7, PTE0–PTE2 VOH VREG –0.8 — — V Output low voltage (ILoad = 1.6 mA) All I/O pins (ILoad = 25 mA) PTD0–PTD1 in ILDD mode (ILoad = 10 mA) PTE3–PTE4 with USB disabled VOL — — — — — — 0.4 0.5 0.4 Input high voltage All ports, OSC1 IRQ, RST VIH 0.7 × VREG 0.
MC68HC08JB8 NOTES: 1. VDD = 4.0 to 5.5 Vdc, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted. 2. Typical values reflect average measurements at midpoint of voltage range, 25 °C only. 3. Run (operating) IDD measured using external square wave clock source (fXCLK = 6 MHz). All inputs 0.2 V from rail. No dc loads. Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects run IDD. Measured with all modules enabled. 4.
MC68HC08JB8 Technical Data 276 MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.
Technical Data — MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 Appendix B. MC68HC08JT8 B.1 Contents B.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 B.3 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 B.4 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 B.5 Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 B.6 Reserved Register Bit. . . . . .
MC68HC08JT8 B.2 Introduction This section introduces the MC68HC08JT8, a low-voltage ROM part version to the MC68HC908JB8. The entire data book apply to this ROM device, with exceptions outlined in this appendix. Table B-1. Summary of MC68HC08JT8 and MC68HC908JB8 Differences MC68HC08JT8 MC68HC908JB8 Memory ($DC00–$FBFF) 8,192 bytes ROM 8,192 bytes FLASH User vectors ($FFF0–$FFFF) 16 bytes ROM 16 bytes FLASH Registers at $FE08 and $FF09 Not used; locations are reserved FLASH related registers.
PTA PTB PTC PTC7–PTC0 (3) PTD PTD7–PTD6 (4) PTD5–PTD2 (4) (5) DDRA DDRB PTB7–PTB0 (3) DDRC CPU REGISTERS PTA7/KBA7 (3) : PTA0/KBA0 (3) ARITHMETIC/LOGIC UNIT (ALU) KEYBOARD INTERRUPT MODULE CONTROL AND STATUS REGISTERS — 64 BYTES TIMER INTERFACE MODULE USER ROM — 8,192 BYTES USER RAM — 256 BYTES BREAK MODULE MONITOR ROM — 464 BYTES DISABLED LOW VOLTAGE INHIBIT MODULE OSC1 OSC2 DDRD USER ROM VECTORS — 16 BYTES PTD1–PTD0 (4) (6) POWER-ON RESET MODULE OSCILLATOR PTE4 (3) (4) (5) (1), (3) I
MC68HC08JT8 $0000 ↓ $003F I/O Registers 64 Bytes $0040 ↓ $013F RAM 256 Bytes $0140 ↓ $DBFF Unimplemented 56,000 Bytes $DC00 ↓ $FBFF ROM 8,192 Bytes $FC00 ↓ $FDFF Unimplemented 512 Bytes $FE00 Break Status Register (BSR) $FE01 Reset Status Register (RSR) $FE02 Reserved $FE03 Break Flag Control Register (BFCR) $FE04 Interrupt Status Register 1 (INT1) $FE05 Reserved $FE06 Reserved $FE07 Reserved $FE08 Reserved $FE09 Reserved $FE0A Reserved $FE0B Reserved $FE0C Break Address
MC68HC08JT8 B.5 Power Supply Pins The MC68HC08JT8 is design for low voltage operation. Connect VDD and VREG for normal operation. The VREG voltage regulator is disabled on the MC68HC08JT8. MCU VDD VREG VSS CBYPASS 0.1 µF + CBULK 10 µF VDD NOTE: Values shown are typical values. Figure B-3. Power Supply Bypassing B.6 Reserved Register Bit Bit 4 of the configuration register ($001F) is a reserved bit on the MC68HC08JT8. The bit will always read as zero.
MC68HC08JT8 B.8 Monitor ROM The monitor program (monitor ROM: $FE10–$FFDF) on the MC68HC08JT8 is for device testing only. $FC00–$FDFF are unused. B.9 Universal Serial Bus Module The USB module is designed for operation with VDD = 4V to 5.5V, therefore, it should not be used on the MC68HC08JT8 device. To further reduce current consumption in stop mode, set the SUSPND bit in the USB interrupt register 0 (UIR0) to logic 1. Other USB registers should be left in their default state. B.
MC68HC08JT8 B.11.2 Functional Operating Range Characteristic Symbol Value Unit TA 0 to 70 °C VDD 2.0 to 3.6 V Operating temperature range Operating voltage range B.11.3 DC Electrical Characteristics Characteristic(1) Symbol Min Typ(2) Max Unit Output high voltage (ILoad = –1.6 mA) PTA0–PTA7, PTB0–PTB7, PTC0–PTC7, PTE0–PTE2 VOH VDD –0.4 — — V Output low voltage (ILoad = 1.6 mA) All I/O pins (ILoad = 15 mA) PTD0–PTD1 in ILDD mode (ILoad = 5 mA) PTE3–PTE4 VOL — — — — — — 0.4 0.5 0.
MC68HC08JT8 NOTES: 1. VDD = 2.0 to 3.6 Vdc, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted. 2. Typical values reflect average measurements at 3V, 25 °C only. 3. In LDD mode, the specified IOL is achieved when the external pullup voltage is equal to or higher than the voltage: VOL + voltage dropped across LED. 4. Run (operating) IDD measured using external square wave clock source (fXCLK = 6 MHz). All inputs 0.2 V from rail. No dc loads. Less than 100 pF on all outputs. CL = 20 pF on OSC2.
How to Reach Us: Home Page: www.freescale.com RoHS-compliant and/or Pb- free versions of Freescale products have the functionality and electrical characteristics of their non-RoHS-compliant and/or non-Pb- free counterparts. For further information, see http://www.freescale.com or contact your Freescale sales representative. E-mail: support@freescale.com For information on Freescale.s Environmental Products program, go to http://www.freescale.com/epp.
