Datasheet

System Integration Module (SIM)
Technical Data MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
108 System Integration Module (SIM) Freescale Semiconductor
8.6.1.2 SWI Instruction
The SWI instruction is a non-maskable instruction that causes an
interrupt regardless of the state of the interrupt mask (I bit) in the
condition code register.
NOTE: A software interrupt pushes PC onto the stack. A software interrupt does
not push PC–1, as a hardware interrupt does.
8.6.2 Interrupt Status Registers
The flags in the interrupt status registers identify maskable interrupt
sources. Table 8-4 summarizes the interrupt sources and the interrupt
status register flags that they set. The interrupt status registers can be
useful for debugging.
Table 8-4. Interrupt Sources
Source Flags
Mask
(1)
INT Register Flag
Priority
(2)
Vector Address
SWI Instruction — 0 $FFFC–$FFFD
USB Reset Interrupt RSTF URSTD
IF2 1 $FFFA–$FFFB
USB Endpoint 0 Transmit TXD0F TXD0IE
USB Endpoint 0 Receive RXD0F RXD0IE
USB Endpoint 1 Transmit TXD1F TXD1IE
USB Endpoint 2 Transmit TXD2F TXD2IE
USB Endpoint 2 Receive RXD2F RXD2IE
USB End of Packet EOPF EOPIE
USB Resume Interrupt RESUMF —
IRQ Interrupt (IRQ
, PTE4)
IRQF
PTE4IF
IMASK IF1 2 $FFF8–$FFF9
TIM Channel 0 CH0F CH0IE IF3 3 $FFF6–$FFF7
TIM Channel 1 CH1F CH1IE IF4 4 $FFF4–$FFF5
TIM Overflow TOF TOIE IF5 5 $FFF2–$FFF3
Keyboard Interrupt KEYF IMASKK IF6 6 $FFF0–$FFF1
1. The I bit in the condition code register is a global mask for all interrupt sources except the SWI instruction.
2. 0 = highest priority