Datasheet

System Integration Module (SIM)
SIM Registers
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Technical Data
Freescale Semiconductor System Integration Module (SIM) 113
Figure 8-17. Stop Mode Recovery from Interrupt or Break
8.8 SIM Registers
The SIM has two break registers and one reset register.
8.8.1 Break Status Register
The break status register contains a flag to indicate that a break caused
an exit from stop or wait mode.
SBSW — SIM Break Stop/Wait
This status bit is useful in applications requiring a return to wait or stop
mode after exiting from a break interrupt. Clear SBSW by writing a
logic 0 to it. Reset clears SBSW.
1 = Stop mode or wait mode was exited by break interrupt
0 = Stop mode or wait mode was not exited by break interrupt
OSCXCLK
INT/BREAK
IAB
STOP + 2 STOP + 2 SP SP – 1 SP – 2 SP – 3STOP +1
STOP RECOVERY PERIOD
Address: $FE00
Bit 7654321Bit 0
Read:
RRRRRR
SBSW
R
Write: Note 1
Reset: 0
Note 1. Writing a logic 0 clears SBSW. R = Reserved
Figure 8-18. Break Status Register (BSR)