Datasheet

Monitor ROM (MON)
Technical Data MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
166 Monitor ROM (MON) Freescale Semiconductor
10.4.1 Entering Monitor Mode
Table 10-1 shows the pin conditions for entering monitor mode. As
specified in the table, monitor mode may be entered after a POR and will
allow communication at 9600 baud provided one of the following sets of
conditions is met:
1. If IRQ = V
DD
+ V
HI
:
– External clock on OSC1 is 3MHz
– PTA3 = low
2. If IRQ = V
DD
+ V
HI
:
– External clock on OSC1 is 6MHz
– PTA3 = high
3. If $FFFE & $FFFF is blank (contains $FF):
– External clock on OSC1 is 6MHz
–IRQ = V
DD
Table 10-1. Mode Entry Requirements and Options
IRQ
$FFFE
and
$FFFF
PTA3 PTA2 PTA1 PTA0
External Clock,
f
XCLK
Bus
Frequency,
f
BUS
Comments
V
DD
+ V
HI
X 0011 3MHz
3MHz
(f
XCLK
)
High-voltage entry to
monitor mode.
9600 baud communication
on PTA0. COP disabled.
V
DD
+ V
HI
X 1011 6MHz
3MHz
(f
XCLK
÷ 2)
V
DD
BLANK
(contain
$FF)
XXX1 6MHz
3MHz
(f
XCLK
÷ 2)
Low-voltage entry to
monitor mode.
9600 baud communication
on PTA0. COP disabled.
V
DD
NOT
BLANK
XXXX 6MHz
3MHz
(f
XCLK
÷ 2)
Enters user mode.
If $FFFE and $FFFF is
blank, MCU will encounter
an illegal address reset.
Notes:
1. PTA3 = 0: Bypasses the divide-by-two prescaler to SIM when using V
DD
+ V
HI
for monitor mode entry.
2. See Section 18. Electrical Specifications
for V
DD
+ V
HI
voltage level requirements.