Datasheet

Computer Operating Properly (COP)
Technical Data MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
238 Computer Operating Properly (COP) Freescale Semiconductor
15.3 Functional Description
Figure 15-1 shows the structure of the COP module.
Figure 15-1. COP Block Diagram
The COP counter is a free-running 6-bit counter preceded by a 12-bit
system integration module (SIM) counter. If not cleared by software, the
COP counter overflows and generates an asynchronous reset after
2
18
–2
4
or 2
13
–2
4
OSCXCLK cycles, depending on the state of the
COP rate select bit, COPRS in the configuration register. With a 2
18
–2
4
OSCXCLK cycle overflow option (COPRS = 0), a 12MHz OSCXCLK
clock (6MHz crystal) gives a COP timeout period of 21.84 ms. Writing
any value to location $FFFF before an overflow occurs prevents a COP
reset by clearing the COP counter and stages 12 through 5 of the SIM
counter.
COPCTL WRITE
OSCXCLK
RESET VECTOR FETCH
SIM RESET CIRCUIT
RESET STATUS REGISTER
INTERNAL RESET SOURCES
(1)
SIM
CLEAR STAGES 5–12
12-BIT SIM COUNTER
CLEAR ALL STAGES
COPD (FROM CONFIG)
RESET
COPCTL WRITE
CLEAR
COP MODULE
COPEN (FROM SIM)
COP COUNTER
NOTE:
1. See SIM section for more details.
COP CLOCK
COP TIMEOUT
COP RATE SEL
(COPRS FROM CONFIG)
6-BIT COP COUNTER