Datasheet

Low Voltage Inhibit (LVI)
Technical Data MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
244 Low Voltage Inhibit (LVI) Freescale Semiconductor
Figure 16-1. LVI Module Block Diagram
16.4 LVI Control Register (CONFIG)
LVID —þLow Voltage Inhibit Disable Bit
1 = Low voltage inhibit disabled
0 = Low voltage inhibit enabled
16.5 Low-Power Modes
The STOP and WAIT instructions put the MCU in low-power
consumption standby modes.
16.5.1 Wait Mode
The LVI module, when enabled, will continue to operate in WAIT Mode.
16.5.2 Stop Mode
The LVI module, when enabled, will continue to operate in STOP Mode.
LOW V
DD
LVI D
DETECTOR
V
DD
LVI RESET
V
DD
> V
LVR
= 0
V
DD
< V
LVR
= 1
Address: $001F
Bit 7654321Bit 0
Read: 0 0
URSTD LVID SSREC COPRS STOP COPD
Write:
Reset:00000000
One-time writable register after each reset. URSTD and LVID bits are reset by POR or LVI reset only.
= Unimplemented
Figure 16-2. Configuration Register (CONFIG)