Datasheet
Electrical Specifications
Control Timing
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3 Technical Data
Freescale Semiconductor Electrical Specifications 257
18.7 Control Timing
18.8 Oscillator Characteristics
NOTES:
1. V
DD
= 4.0 to 5.5 Vdc, V
SS
= 0 Vdc, T
A
= T
L
to T
H
, unless otherwise noted.
2. Typical values reflect average measurements at midpoint of voltage range, 25 °C only.
3. Run (operating) I
DD
measured using external square wave clock source (f
XCLK
= 6 MHz). All inputs 0.2 V from rail. No dc
loads. Less than 100 pF on all outputs. C
L
= 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly
affects run I
DD
. Measured with all modules enabled.
4. Wait I
DD
measured using external square wave clock source (f
XCLK
= 6 MHz); all inputs 0.2 V from rail; no dc loads; less
than 100 pF on all outputs. C
L
= 20 pF on OSC2; 15 kΩ ± 5% termination resistors on D+ and D– pins; all ports configured
as inputs; OSC2 capacitance linearly affects wait I
DD
5. STOP I
DD
measured with USB in suspend mode; OSC1 grounded; transceiver pullup resistor of 1.5 kΩ ± 5% between V
REG
and D– and 15 kΩ ± 5% termination resistors on D+ and D– pins; no port pins sourcing current.
6. Maximum is highest voltage that POR is guaranteed.
7. If minimum V
REG
is not reached before the internal POR reset is released, RST must be driven low externally until minimum
V
REG
is reached.
Characteristic
(1)
NOTES:
1. V
DD
= 4.0 to 5.5 Vdc; V
SS
= 0 Vdc; timing shown with respect to 20% V
DD
and 70% V
DD
, unless otherwise noted.
Symbol Min Max Unit
Internal operating frequency
(2)
2. Some modules may require a minimum frequency greater than dc for proper operation; see appropriate table for this infor-
mation.
f
OP
—3MHz
RST
input pulse width low
(3)
3. Minimum pulse width reset is guaranteed to be recognized. It is possible for a smaller pulse width to cause a reset.
t
IRL
125 — ns
Characteristic Symbol Min Typ Max Unit
Crystal frequency
(1)
NOTES:
1. The USB module is designed to function at f
XCLK
= 6 MHz.
f
XCLK
1— 6 MHz
External clock
Reference frequency
(1), (2)
2. No more than 10% duty cycle deviation from 50%.
f
XCLK
dc — 6 MHz
Crystal load capacitance
(3)
3. Consult crystal vendor data sheet.
C
L
—— —
Crystal fixed capacitance
(3)
C
1
—
2
×
C
L
—
Crystal tuning capacitance
(3)
C
2
—
2
×
C
L
—
Feedback bias resistor
R
B
—10 MΩ —
Series resistor
(3), (4)
4. Not required for high-frequency crystals.
R
S
—— —