Datasheet

Electrical Specifications
Technical Data MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
260 Electrical Specifications Freescale Semiconductor
18.11 USB Signaling Levels
18.12 TImer Interface Module Characteristics
Bus State
Signaling Levels
Transmit Receive
Differential 1
D+ > V
OH
(min) and D– < V
OL
(max)
(D+) – (D–) > 200 mV
Differential 0
D– > V
OH
(min) and D– < V
OL
(max)
(D–) – (D+) > 200 mV
Single-ended 0 (SE0)
D+ and D– < V
OL
(max) D+ and D– < V
IL
(max)
Data J state (low speed) Differential 0 Differential 0
Data K state (low speed) Differential 1 Differential 1
Idle state (low speed) NA
D– > V
IHZ
(min) and D+ < V
IL
(max)
Resume state Differential 1 Differential 1
Start of packet (SOP) Data lines switch from Idle to K State
End of packet (EOP)
SE0 for approximately 2 bit times
(1)
followed by a J state for 1 bit time
NOTES:
1. The width of EOP is defined in bit times relative to the speed of transmission.
SE0 for ≥ 1 bit time
(2)
followed by a
J state for 1 bit time
2. The width of EOP is defined in bit times relative to the device type receiving the EOP. The bit time is approximate.
Reset NA
D+ and D– < V
IL
(max) for ≥ 8µs
Characteristic Symbol Min Max Unit
Input capture pulse width
t
TIH,
t
TIL
1/f
OP
—
Input clock pulse width
t
TCH,
t
TCL
(1/f
OP
) + 5ns
—