Datasheet

System Integration Module (SIM)
Technical Data MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
96 System Integration Module (SIM) Freescale Semiconductor
8.3 SIM Bus Clock Control and Generation
The bus clock generator provides system clock signals for the CPU and
peripherals on the MCU. The system clocks are generated from an
incoming clock, OSCOUT, as shown in Figure 8-3.
Figure 8-3. SIM Clock Signals
Addr.Register Name Bit 7654321Bit 0
$FE00 Break Status Register
(BSR)
Read:
RRRRRR
SBSW
R
Write: See note
Reset: 0
Note: Writing a logic 0 clears SBSW.
$FE01 Reset Status Register
(RSR)
Read: POR PIN COP ILOP ILAD USB LVI 0
Write:
POR:10000000
$FE02 Reserved Read:
RRRRRRRR
Write:
$FE03 Break Flag Control
Register
(BFCR)
Read:
BCFERRRRRRR
Write:
Reset: 0
$FE04 Interrupt Status Register 1
(INT1)
Read: IF6 IF5 IF4 IF3 IF2 IF1 0 0
Write:RRRRRRRR
Reset:00000000
Figure 8-2. SIM I/O Register Summary
÷ 2
BUS CLOCK
GENERATORS
SIM
SIM COUNTER
FROM CLOCK
DOUBLER
FROM CLOCK
DOUBLER
OSCOUT
OSCXCLK