Datasheet

I/O Registers
MC68HC908JL3E Family Data Sheet, Rev. 4
Freescale Semiconductor 101
ADCO — ADC Continuous Conversion Bit
When set, the ADC will convert samples continuously and update the ADR register at the end of each
conversion. Only one conversion is allowed when this bit is cleared. Reset clears the ADCO bit.
1 = Continuous ADC conversion
0 = One ADC conversion
ADCH[4:0] — ADC Channel Select Bits
ADCH[4:0] form a 5-bit field which is used to select one of the ADC channels. The five channel select
bits are detailed in the following table. Care should be taken when using a port pin as both an analog
and a digital input simultaneously to prevent switching noise from corrupting the analog signal.
The ADC subsystem is turned off when the channel select bits are all set to one. This feature allows
for reduced power consumption for the MCU when the ADC is not used. Reset sets all of these bits to
a1.
NOTE
Recovery from the disabled state requires one conversion cycle to stabilize.
Table 9-1. MUX Channel Select
ADCH4 ADCH3 ADCH2 ADCH1 ADCH0 ADC Channel Input Select
00000 ADC0 PTB0
00001 ADC1 PTB1
00010 ADC2 PTB2
00011 ADC3 PTB3
00100 ADC4 PTB4
00101 ADC5 PTB5
00110 ADC6 PTB6
00111 ADC7 PTB7
01000 ADC8 PTD3
01001 ADC9 PTD2
01010ADC10 PTD1
01011ADC11 PTD0
01100
Unused
(see Note 1)
::::: —
11010
11011 — Reserved
11
1 0 0 — Unused
11
1 0 1
V
DDA
(see Note 2)
11
1 1 0
V
SSA
(see Note 2)
11
1 1 1 ADC power off
1. If any unused channels are selected, the resulting ADC conversion will be unknown.
2. The voltage levels supplied from internal reference nodes as specified in the table are used to verify the
operation of the ADC converter both in production test and for user applications.