Datasheet

Input/Output (I/O) Ports
MC68HC908JL3E Family Data Sheet, Rev. 4
104 Freescale Semiconductor
$000A
Port D Control Register
(PDCR)
Read:0000
SLOWD7 SLOWD6 PTDPU7 PTDPU6
Write:
Reset:00000000
$000D
Port A Input Pull-up Enable
Register
(PTAPUE)
Read:
PTA6EN PTAPUE6 PTAPUE5 PTAPUE4 PTAPUE3 PTAPUE2 PTAPUE1 PTAPUE0
Write:
Reset:00000000
= Unimplemented
Table 10-1. Port Control Register Bits Summary
Port Bit DDR
Module Control
Pin
Module Register
Control Bit
A
0 DDRA0
KBI KBIER ($001B)
KBIE0 PTA0/KBI0
1 DDRA1 KBIE1 PTA1/KBI1
2 DDRA2 KBIE2 PTA2/KBI2
3 DDRA3 KBIE3 PTA3/KBI3
4 DDRA4 KBIE4 PTA4/KBI4
5 DDRA5 KBIE5 PTA5/KBI5
6 DDRA6
OSC
KBI
PTAPUE ($000D)
KBIER ($001B)
PTA6EN
KBIE6
RCCLK/PTA6/KBI6
(1)
1. RCCLK/PTA6/KBI6 pin is only available on MC68HRC908JL3E/JK3E/JK1E devices (RC option);
PTAPUE register has priority control over the port pin.
RCCLK/PTA6/KBI6 is the OSC2 pin on MC68HC908JL3E/JK3E/JK1E devices (X-TAL option).
B
0 DDRB0
ADC ADSCR ($003C) ADCH[4:0]
PTB0/ADC0
1 DDRB1 PTB1/ADC1
2 DDRB2 PTB2/ADC2
3 DDRB3 PTB3/ADC3
4 DDRB4 PTB4/ADC4
5 DDRB5 PTB5/ADC5
6 DDRB6 PTB6/ADC6
7 DDRB7 PTB7/ADC7
D
0 DDRD0
ADC ADSCR ($003C) ADCH[4:0]
PTD0/ADC11
1 DDRD1 PTD1/ADC10
2 DDRD2 PTD2/ADC9
3 DDRD3 PTD3/ADC8
4 DDRD4
TIM
TSC0 ($0025) ELS0B:ELS0A PTD4/TCH0
5 DDRD5 TSC1 ($0028) ELS1B:ELS1A PTD5/TCH1
6 DDRD6 — — — PTD6
7 DDRD7 — — — PTD7
Addr.Register Name Bit 7654321Bit 0
Figure 10-1. I/O Port Register Summary