Datasheet

External Interrupt (IRQ)
MC68HC908JL3E Family Data Sheet, Rev. 4
114 Freescale Semiconductor
The vector fetch or software clear may occur before or after the interrupt pin returns to one. As long as
the pin is low, the interrupt request remains pending. A reset will clear the latch and the MODE control bit,
thereby clearing the interrupt even if the pin stays low.
When set, the IMASK bit in the INTSCR mask all external interrupt requests. A latched interrupt request
is not presented to the interrupt priority logic unless the IMASK bit is clear.
NOTE
The interrupt mask (I) in the condition code register (CCR) masks all
interrupt requests, including external interrupt requests. See 5.5 Exception
Control.
Figure 11-1. IRQ Module Block Diagram
Addr.Register Name Bit 7654321Bit 0
$001D
IRQ Status and Control
Register (INTSCR)
Read:0000IRQF0
IMASK MODE
Write:
ACK
Reset:00000000
= Unimplemented
Figure 11-2. IRQ I/O Register Summary
ACK
IMASK
DQ
CK
CLR
IRQ
HIGH
INTERRUPT
TO MODE
SELECT
LOGIC
IRQ
FF
REQUEST
V
DD
MODE
VOLTAGE
DETECT
SYNCHRO-
NIZER
IRQF
TO CPU FOR
BIL/BIH
INSTRUCTIONS
VECTOR
FETCH
DECODER
INTERNAL ADDRESS BUS
RESET
V
DD
IRQ
IRQPUD
INTERNAL
PULLUP
DEVICE